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Intel 855PM Design Manual

Intel 855PM Design Manual

Chipset platform for use with pentium m and celeron m processors
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®
Intel
855PM Chipset Platform
Design Guide
For use with Intel
Pentium
M and Intel
Celeron
M Processors
®
®
®
®
May 2004
Revision Number 003
Document Number:
252614-003

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Summary of Contents for Intel 855PM

  • Page 1 ® Intel 855PM Chipset Platform Design Guide For use with Intel Pentium M and Intel Celeron M Processors ® ® ® ® May 2004 Revision Number 003 Document Number: 252614-003...
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    4.1.4.1.3. Topology 1C: Open Drain (OD) Signals Driven by the Processor – PROCHOT#..........54 4.1.4.1.4. Topology 2A: Open Drain (OD) Signal Driven by Intel 82801DBM ICH4-M – PWRGOOD .......55 4.1.4.1.5. Topology 2B: CMOS Signals Driven by Intel 82801DBM ICH4-M – DPSLP#............56 ®...
  • Page 4 4.3.3.1. Mechanical Considerations ............88 4.3.3.2. Electrical Considerations ..............88 4.4. Intel Pentium M Processor / Intel Celeron M Processor and Intel 855PM MCH FSB Signal Package Lengths ....................88 Platform Power Requirements ....................91 5.1. General Description....................... 91 5.2.
  • Page 5 Voltage Plane and Decoupling......114 5.9.4.2. Intel 855PM MCH V Voltage Plane and Decoupling....118 5.9.5. Intel 855PM MCH Core Voltage Plane and Decoupling ......119 System Memory Design Guidelines (DDR-SDRAM)..............125 6.1. DDR 200/266/333 MHz System Memory Topology and Layout Design Guidelines ...126 6.1.1.
  • Page 6 6.3. DDR System Memory Interface Strapping ..............161 6.4. ECC Disable Guidelines....................161 6.4.1. Intel 855PM MCH ECC Functionality Disable ..........161 6.4.2. DDR Memory ECC Functionality Disable............ 162 6.5. System Memory Compensation .................. 162 6.6. SMVREF Generation....................162 6.7.
  • Page 7 9.8.8. RTC-Well Input Strap Requirements ............211 9.9. Internal LAN Layout Guidelines ...................212 9.9.1. Footprint Compatibility .................212 9.9.2. Intel 82801DBM ICH4-M – LAN Connect Interface Guidelines ....213 9.9.2.1. Bus Topologies ................213 9.9.2.1.1. LOM (LAN On Motherboard) Point-To-Point Interconnect ..............214 9.9.2.2. Signal Routing and Layout............214 ®...
  • Page 8 CLK14 Clock Group..................243 10.2.8. CK-408 Clock Chip Decoupling ..............243 10.3. CK-408 Updates for Systems based on Intel Pentium M Processor / Intel Celeron M Processor and Intel 855PM Chipset ................244 10.4. CK-408 PWRDWN# Signal Connections ..............244 Platform Power Delivery Guidelines ..................
  • Page 9 RF Disable Support Requirements for Intel PRO/Wireless 2100 and Bluetooth Devices....................272 Reserved, NC, and Test Signals ....................273 13.1. Intel Pentium M Processor and Intel Celeron M RSVD Signals ........273 13.2. Intel 855PM MCH RSVD Signals.................274 Platform Design Checklist ......................275 14.1.
  • Page 10 14.5. CK-408 Clock Checklist....................290 14.5.1. Resistor Recommendations ................ 290 14.5.2. CK-408 Decoupling Recommendation ............292 14.6. Intel 855PM MCH Checklist ..................293 14.6.1. System Memory................... 293 14.6.1.1. MCH System Memory Interface ........... 293 14.6.1.2. DDR SO-DIMM Interface.............. 296 14.6.2.
  • Page 11 Figure 4. Trace Spacing vs. Trace Width Example..............34 Figure 5. Recommended Stack-up Capacitive Coupling Model ..........35 Figure 6. Common Clock Signals Example – Intel 855PM MCH Escape Routing ....39 Figure 7. Common Clock Signals Example – Processor Escape Routing......39 Figure 8.
  • Page 12 Figure 47. Intel® Pentium® M Processor / Intel® Celeron® M Processor VID[5:0] Escape Routing Layout Example ..................95 Figure 48. Power On Sequencing Timing Diagram ..............97 Figure 49. V Block Diagram ....................98 Figure 50. V Block Diagram.................... 98 CC-MCH Figure 51.
  • Page 13 Figure 125. Ground Plane Separation................... 223 Figure 126. RTC Power Well Isolation Control ..............226 Figure 127. Intel 82801DBM ICH4-M CPU CMOS Signals with CPU and FWH ....227 Figure 128. Platform Clock Topology Diagram ..............231 Figure 129. Source Shunt Termination Topology ..............232 Figure 130.
  • Page 14 Figure 152. Clock Power Down Implementation..............292 Figure 153. Reference Voltage Level for SMVREF[1:0] ............295 Figure 154. Intel 855PM MCH HSWNG[1:0] Reference Voltage Generation Circuit ... 299 Figure 155. Intel 855PM MCH HVREF[4:0] Generation Circuit..........299 Figure 156. AGPREF Implementation (On Intel CRB)............305 Figure 157.
  • Page 15 Table 34. Existing PC2100/PC1600 DDR SDRAM Design Guidelines Required for PC2700 Support ....................159 Table 35. Intel 855PM Chipset DDR Signal Package Lengths ..........160 Table 36. AGP 2.0 Signal Groups ..................168 Table 37. AGP 2.0 Data/Strobe Associations ............... 169 Table 38.
  • Page 16 Table 84. Intel 855PM MCH Power Consumption Estimates ..........268 Table 85. Intel 82801DBM ICH4-M Power Consumption Estimates ........269 Table 86. Intel 855PM MCH Component Thermal Design Power ......... 270 Table 87. Intel 82801DBM ICH4-M Component Thermal Design Power ......270 Table 88.
  • Page 17 Incorporated information from Design Guide Update 253479-002 Updated design guidelines for supporting PC2700 (333 MHz) DDR SDRAM Transition from Intel 855PM DDR 266/200 MHz Chipset to Intel 855PM DDR 200/266/333 MHz Chipset Design Guidelines System Memory SMVREF Design Update ®...
  • Page 18 This page intentionally left blank. ® Intel 855PM Chipset Platform Design Guide...

  • Page 19: Introduction

    This design guide organizes and provides Intel’s design recommendations for systems incorporating the ® Intel 855PM chipset. These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. The Intel 855PM chipset supports the ® ® ®...
  • Page 20 Introduction Convention/Terminology Definition Low Speed – Refers to USB 1.0 Low Speed Modem Codec Intel’s next generation chipset memory controller hub for mobile platforms Pulse Code Modulation Platform LAN Connect Real Time Clock SMBus System Management Bus – A two-wire interface through which various system...

  • Page 21: Referenced Documents

    Introduction 1.2. Referenced Documents Contact your Intel Field Representatives for the latest revisions. Document Location http://developer.intel.com ® ® Intel Pentium M Processor on 90nm process with 2-MB L2 Cache Datasheet ® ® http://developer.intel.com Intel Pentium M Processor Datasheet http://developer.intel.com ®...
  • Page 22 Introduction This page intentionally left blank. ® Intel 855PM Chipset Platform Design Guide...

  • Page 23: System Overview

    The integrated Wi-Fi Certified Intel PRO/Wireless Network Connection has been designed and validated to work with all of the Intel Centrino mobile technology components and is able to connect to 802.11 Wi-Fi certified access points. It also supports advanced wireless LAN security including Cisco* LEAP, 802.1X, and WEP in addition to providing software-upgradeable support for future security...

  • Page 24: Figure 1. Basic System Block Diagram

    MHz DDR Controller FCBGA PCI Bus Interface USB2.0/1.1 (6) ® Mini PCI Intel 82801DBM IDE (2) 421 BGA ® (ICH4-M) Intel PRO/Wireless Devices LAN PHY Network Connection AC97 Codecs LPC I/F Super I/O ® Intel 855PM Chipset Platform Design Guide...

  • Page 25: Intel Pentium M Processor/Intel Celeron M Processor

    CC-CORE VCCA: Intel Pentium M processor and Intel Celeron M processor: 1.8 V Intel Pentium M processor on 90nm process with 2-MB L2 Cache: 1.8 V or 1.5 V (1.05 V) 2.3. Intel 855PM Memory Controller Hub (MCH) 2.3.1.

  • Page 26: Integrated System Memory Dram Controller

    AGP Clamping and Sense Amp control 2.3.4. Packaging/Power 593-pin, Micro-FCBGA package (37.5 mm x 37.5 mm) (1.2 V); VCCSM (2.5 V); 1.5 V; VCCGA, VCCHA, & VCC1_8 (1.8 V); V (1.05 V) CC-MCH ® Intel 855PM Chipset Platform Design Guide...

  • Page 27: Intel 82801Dbm I/O Controller Hub (Ich4-M)

    System Overview 2.4. Intel 82801DBM I/O Controller Hub (ICH4-M) The Intel 82801DBM provides the I/O subsystem with access to the rest of the system: Upstream Accelerated Hub Architecture interface for access to the MCH PCI 2.2 interface (6 PCI Request/Grant Pairs) Bus Master IDE controller (supports Ultra ATA 100/66/33) USB 1.1 and USB 2.0 Host Controllers and support for USB 2.0 High Speed Debug port...

  • Page 28: Packaging And Power

    Mini-PCI Type 3A: (59.45 mm x 50.8 mm x 5 mm) 3.3V 2.6. Firmware Hub (FWH) An integrated hardware Random Number Generator (RNG) Register-based locking Hardware-based locking Five GPIs 2.6.1. Packaging/Power 32-pin TSOP/PLCC 3.3-V core and 3.3 V/12 V for fast programming ® Intel 855PM Chipset Platform Design Guide...

  • Page 29: General Design Considerations

    If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations are completed for each design. Even when the guidelines are followed, Intel recommends that critical signals be simulated to ensure proper signal integrity and flight time. Any deviation from the guidelines should be simulated.

  • Page 30: Figure 2. Recommended Board Stack-Up Dimensions

    2. Power plane layers should be 1 oz thick and signal layers should be ½ oz thick. 3. External layers become 1 – 1.5 oz (1.2 – 2 mils) thick after plating ® Intel 855PM Chipset Platform Design Guide...
  • Page 31 Due to the arrangement of the Intel® Pentium® M Processor / Intel® Celeron® M Processor and Intel 855PM MCH pin-maps, GND vias placed near all GND lands will also be very close to high-speed signals that may be transitioning to an internal layer. Thus, no additional...
  • Page 32 General Design Considerations This page intentionally left blank. ® Intel 855PM Chipset Platform Design Guide...

  • Page 33: Fsb Design Guidelines

    The following layout guidelines support designs using the Intel Pentium M processor / Intel Celeron M processor and the Intel 855PM MCH chipset. Due to on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be placed on the motherboard for most FSB signals. A simple point-to-point interconnect topology is used in these cases.

  • Page 34: Trace Space To Trace Width Ratio

    As shown in Figure 5, the coupling values are calculated based on a three-line model, represented by Trace 1, Trace 2, and Trace 3. Based on the capacitive coupling model shown, the aforementioned parameters are: = C21 + C23 MUTUAL ® Intel 855PM Chipset Platform Design Guide...

  • Page 35: Signal Propagation Time To Distance Relationship And Assumptions

    “typical” stack-up assumptions. Finally, in cases that need to account for worst-case stack-up parameters and for even or odd mode coupling, new extractions from the stack-up model must be done to provide an accurate signal propagation time to distance relationship. ® Intel 855PM Chipset Platform Design Guide...

  • Page 36: Common Clock Signals

    6.5 inches. Trace length matching for the common clock signals is not required. Intel recommends routing these signals on the same internal or external layer for the entire length of the bus. If routing constraints require routing of these signals with a transition to a different layer, a minimum of one ground stitching via for every two signals should be placed within 100 mils of the signal transition vias.

  • Page 37: Table 1. Fsb Common Clock Signal Internal Layer Routing Guidelines

    55 ± 15% 4 & 8 RESET# CPURST# Strip-line 55 ± 15% 4 & 8 NOTE: For topologies where an ITP700FLEX debug port is implemented, see Section 4.1.5 for RESET# (CPURST#) implementation details. ® Intel 855PM Chipset Platform Design Guide...

  • Page 38: Table 2. Fsb Common Clock Signal External Layer Routing Guidelines

    55 ± 15% 5 & 10 RESET# CPURST# Micro-strip 55 ± 15% 5 & 10 NOTE: For topologies where an ITP700FLEX debug port is implemented, see Section 4.1.5 for RESET# (CPURST#) implementation details. ® Intel 855PM Chipset Platform Design Guide...

  • Page 39: Figure 6. Common Clock Signals Example - Intel 855Pm Mch Escape Routing

    FSB Design Guidelines Figure 6. Common Clock Signals Example – Intel 855PM MCH Escape Routing PRIMARY SIDE Layer 6 COMMON Clock Signals DPSLP# RESET# Figure 7. Common Clock Signals Example – Processor Escape Routing Layer 6 DPSLP# RESET# COMMON Clock Signals ®...

  • Page 40: Figure 8. Common Clock Signals Example - Processor To Intel 855Pm Mch Layer 6 Routing

    FSB Design Guidelines Figure 8. Common Clock Signals Example – Processor to Intel 855PM MCH Layer 6 Routing Mother Board Layer 6 routing Mother Board Layer 6 routing Mother Board Layer 6 routing Mother Board Layer 6 routing Mother Board Layer 6 routing...

  • Page 41: Source Synchronous Signals

    FSB signals are routed. In addition all the ground plane areas are stitched with ground vias in the vicinity of the processor and Intel 855PM MCH package outlines with the vias of the ground pins of the processor and MCH pin-map.

  • Page 42: Figure 9. Layer 6 Fsb Source Synchronous Signals Gnd Referencing

    FSB signals routing between the processor and MCH. Figure 10. Layer 3 FSB Source Synchronous Signals GND Referencing to Layer 2 and Layer 4 Ground Planes Stackup cross-section L3 and L4 top side view BSB DATA BSB ADDRESS 100MHz CLKs ® Intel 855PM Chipset Platform Design Guide...

  • Page 43: Source Synchronous - Data

    ± 100 mils of the associated strobes. Because the processor and Intel 855PM MCH packages provide package trace equalization for signals within each data group, all signals should be routed on the system board to meet the pin-to-pin matching requirement of ±...

  • Page 44: Source Synchronous - Address

    In addition, each address signal should be trace length matched within ± 200 mils of its associated strobe signal. ® Intel 855PM Chipset Platform Design Guide...

  • Page 45: Source Synchronous Signals Recommended Layout Example

    VCCA (1.8 V) power plane to the PLL power delivery pins VCCGA and VCCHA of the Intel 855PM MCH and continues to the VCCA[3:0] pins of the processor. Notice that this 1.8-V VCCA power plane “forks” as a separate branch from the 1.8-V decoupling capacitor while the Hub Interface (HI) 1.8-V power pins connect to a separate branch of the 1.8-V...
  • Page 46 Source synchronous signals are serpentine length matched on Layer 3 and Layer 6 in the area in between the processor and Intel 855PM MCH packages per the procedure described in Section 4.1.3.5. Also, the source synchronous address signals route around the thermal backing plate hole and utilize the space on Layer 3 and Layer 6 in the socket vicinity to perform trace length equalization.

  • Page 47: Figure 11. Intel 855Pm Mch Source Synchronous Signals Recommended Escape Routing Example

    FSB Design Guidelines Figure 11. Intel 855PM MCH Source Synchronous Signals Recommended Escape Routing Example PRIMARY SIDE PRIMARY SIDE LAYER 3 LAYER 3 D[47:32]# D[47:32]# D[15:0]# D[15:0]# VCCGA VCCGA VCCHA VCCHA 1.8v Decap 1.8v Decap VCCA=1.8v VCCA=1.8v A[16:3]#, REQ*# A[16:3]#, REQ*#...

  • Page 48: Figure 12. Processor Source Synchronous Signals Recommended Escape Routing Example

    D[63:48]# D[63:48]# D[63:48]# VCC-CORE VCC-CORE VCC-CORE D[31:16]# D[31:16]# D[31:16]# VCC-CORE VCC-CORE VCC-CORE VCCP VCCP VCCP VCCA=1.8v VCCA=1.8v VCCA=1.8v A[31:17]# A[31:17]# A[31:17]# VIAS to L3 VIAS to L3 VIAS to L3 VIAS to L3 ® Intel 855PM Chipset Platform Design Guide...

  • Page 49: Figure 13. Processor To Intel 855Pm Mch Source Synchronous Signals Routing Example

    FSB Design Guidelines Figure 13. Processor to Intel 855PM MCH Source Synchronous Signals Routing Example Pentium M Pentium M Pentium M Pentium M Pentium M Pentium M Pentium M Pentium M Pentium M Pentium M Pentium M Pentium M Pentium M...

  • Page 50: Trace Length Equalization Procedures

    Record the length in cell B2 of the Excel* spreadsheet. 6. Use the Allegro* “Cut” command to cut the trace in two locations of the serpentine as shown in Figure 15. This will generate a floating section of the serpentine. ® Intel 855PM Chipset Platform Design Guide...

  • Page 51: Asynchronous Signals

    Open Drain signals are pulled-up to a voltage higher than V , the reliability and power consumption of the processor may be affected. Therefore, it is very important to follow the recommended pull-up voltage for these signals. ® Intel 855PM Chipset Platform Design Guide...

  • Page 52: Topology 1A: Open Drain (Od) Signal Driven By The Processor - Ierr

    Table 8. Layout Recommendations for Topology 1A Transmission Line Type 0.5” – 12.0” 0” – 3.0” 0” – 3.0” ± 5% ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0” – 3.0” ± 5% ± 5% Strip-line ® Intel 855PM Chipset Platform Design Guide...

  • Page 53: Topology 1B: Open Drain (Od) Signals Driven By The Processor - Ferr# And Thermtrip

    Rtt is V (1.05 V). Intel recommends that the FERR# signal of the processor be routed to the FERR# signal of the Intel 82801DBM ICH4-M. THERMTRIP# can be implemented in a number of ways to meet design goals. It can be routed to the ICH4-M or any optional system receiver.

  • Page 54: Topology 1C: Open Drain (Od) Signals Driven By The Processor - Prochot

    Rtt is V (1.05 V). Intel recommends that PROCHOT# be routed using the voltage translation logic shown in Figure 18. The receiver at the output of the voltage translation circuit can be any system receiver that can function properly with the PROCHOT# signal given the nature and usage model of this pin. PROCHOT# is capable of toggling hundreds of times per second to signal a hot temperature condition.

  • Page 55: Topology 2A: Open Drain (Od) Signal Driven By Intel 82801Dbm Ich4-M - Pwrgood

    Topology 2A: Open Drain (OD) Signal Driven by Intel 82801DBM ICH4-M – PWRGOOD The Topology 2A OD signal PWRGOOD driven by the Intel 82801DBM ICH4-M (processor CMOS signal input) should adhere to the following routing and layout recommendations. Table 11 lists the recommended routing requirements for the PWRGOOD signal of the processor.

  • Page 56: Topology 2B: Cmos Signals Driven By Intel 82801Dbm Ich4-M - Dpslp

    DPSLP# signal should be routed point-to-point with the daisy chain topology shown. The routing of DPSLP# at the processor should fork out to both the ICH4-M and the Intel 855PM MCH. Segments L1 and L2 from Figure 20 should not T-split from a trace from the processor pin.

  • Page 57: Figure 21. Dpslp# Layout Routing Example

    Intel 855PM Intel 855PM MCH-M MCH-M MCH-M MCH-M DPSLP# DPSLP# DPSLP# DPSLP# From From From From From From Intel Intel ICH4-M ICH4-M ICH4-M ICH4-M Secondary Side Secondary Side Secondary Side Secondary Side ICH4-M ICH4-M ® Intel 855PM Chipset Platform Design Guide...

  • Page 58: Topology 2C: Cmos Signals Driven By Intel 82801Dbm Ich4-M - Lint0/Intr, Lint1/Nmi, A20M#, Ignne#, Slp#, Smi#, And Stpclk

    The Topology 2C CMOS LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK# signals should implement a point-to-point connection between the Intel 82801DBM ICH4-M and the processor. The routing guidelines allow both signals to be routed as either micro-strip or strip-lines using 55 ±...

  • Page 59: Topology 3: Cmos Signals Driven By Intel 82801Dbm Ich4-M To Processor And Fwh - Init

    FSB Design Guidelines 4.1.4.1.7. Topology 3: CMOS Signals Driven by Intel 82801DBM ICH4-M to Processor and FWH – INIT# The signal INIT# should adhere to the following routing and layout recommendations. Table 14 lists the recommended routing requirements for the INIT# signal of the ICH4-M. The routing guidelines allow both signals to be routed as either micro-strip or strip-lines using 55 ±...

  • Page 60: Voltage Translation Logic

    4.1.5. Processor RESET# Signal The RESET# signal is a common clock signal driven by the Intel 855PM MCH CPURST# pin. In a production system where no ITP700FLEX debug port is implemented, a simple point-to-point connection between the CPURST# pin of the MCH and processor’s RESET# pin is recommended (see Figure 25).

  • Page 61: Figure 25. Processor Reset# Signal Routing Topology With No Itp700Flex Connector

    Figure 26. Processor RESET# Signal Routing Topology With ITP700FLEX Connector Intel Pentium M processor Intel 855PM RESET# CPURESET# VCCP ITPFLEX CONNECTOR RESET# ® Intel 855PM Chipset Platform Design Guide...

  • Page 62: Processor Reset# Routing Example

    Figure 27 illustrates a board routing example for the RESET# signal with an ITP700FLEX debug port implemented. Figure 27 illustrates how the CPURST# pin of Intel 855PM MCH forks out into two branches on Layer 6 of the motherboard. One branch is routed directly to the processor’s RESET# pin amongst the rest of the common clock signals.

  • Page 63: Processor And Intel 855Pm Mch Host Clock Signals

    Processor and Intel 855PM MCH Host Clock Signals Figure 28 illustrates processor and Intel 855PM MCH host clock signal routing. Both the processor and the MCH’s BCLK[1:0] signals are initially routed from the CK-408 clock generator on Layer 3. Figure 13 shows how vertical routing on both Layer 3 and Layer 6 is blocked by the FSB address signals’...

  • Page 64: Figure 28. Processor And Intel 855Pm Mch Host Clock Layout Routing Example

    FSB Design Guidelines Figure 28. Processor and Intel 855PM MCH Host Clock Layout Routing Example Secondary Secondary Secondary Secondary Pentium M Pentium M Pentium M Pentium M Intel Pentium M Intel Pentium M Intel Pentium M Intel Pentium M processor...

  • Page 65: Gtlref Layout And Routing Recommendations

    GTLREF networks. Figure 29 shows the recommended topology for generating GTLREF for Intel Pentium M processor using a R1 = 1 k ± 1% and R2 = 2 k ± 1% resistive divider. Since the input buffer trip point is set by the 2/3* V on GTLREF and to allow tracking of V voltage fluctuations, no decoupling should be placed on the GTLREF pin.

  • Page 66: Figure 30. Processor Gtlref Motherboard Layout

    Pin G1 PRIMARY SIDE PRIMARY SIDE A recommended MCH_GTLREF generation circuit for the Intel 855PM MCH is shown in Figure 31. The circuit includes a resistive divider network with R1 = 49.9 ± 1% and R2 = 100 ± 1% and three decoupling capacitors C1 = C2 = 200 pF and C3 = 1 F all bypassed to GND.

  • Page 67: Figure 31. Intel 855Pm Mch Hvref[4:0] Reference Voltage Generation Circuit

    FSB Design Guidelines Figure 31. Intel 855PM MCH HVREF[4:0] Reference Voltage Generation Circuit +VCCP Ω MCH_GTLREF AB16 HVREF Intel AB12 HVREF 855PM Ω HVREF 200 pF 200 pF 1 uF HVREF HVREF A recommended layout for the MCH_GTLREF generation circuit is shown in Figure 32. The MCH_GTLREF generation circuit components are located on the secondary side to minimize motherboard space usage and optimize robustness of the connection.

  • Page 68: Figure 32. Intel 855Pm Mch Hvref[4:0] Motherboard Layout

    FSB Design Guidelines Figure 32. Intel 855PM MCH HVREF[4:0] Motherboard Layout PRIMARY SIDE 1.8v LAYER 3 MCH_GTLREF SECONDARY SIDE PRIMARY SIDE MCH_GTLREF ® Intel 855PM Chipset Platform Design Guide...

  • Page 69: Agtl+ I/O Buffer Compensation

    4.1.8. AGTL+ I/O Buffer Compensation The processor has four pins, COMP[3:0], and the Intel 855PM MCH has two pins, HRCOMP[1:0], that require compensation resistors to adjust the AGTL+ I/O buffer characteristics to specific board and operating environment characteristics. Also, the MCH requires two special reference voltage generation circuits to pins HSWNG[1:0] for the same purpose described above.

  • Page 70: Figure 33. Processor Comp[3:0] Resistor Layout

    One GND Via One GND Via VCCA=1.8v VCCA=1.8v PRIMARY SIDE SECONDARY SIDE Figure 34. Processor COMP[1:0] Resistor Alternative Primary Side Layout PRIMARY SIDE PRIMARY SIDE VCCA=1.8v VCCA=1.8v COMP[1] COMP[1] VCCP VCCP COMP[0] COMP[0] ® Intel 855PM Chipset Platform Design Guide...

  • Page 71: Intel 855Pm Mch Agtl+ I/O Buffer Compensation

    Also, the routing for HRCOMP should be at least 25 mils away from any switching signal. Figure 36 illustrates the recommended layout for the Intel 855PM MCH HRCOMP[1:0] resistors that are placed on the motherboard’s secondary side to save space as well as to make the shortest possible connection without interacting with FSB routing.

  • Page 72: Figure 36. Intel 855Pm Mch Hrcomp[1:0] Resistor Layout

    0.5 inches of their respective pins and connected with a 15-mil wide trace. To avoid coupling with any other signals, maintain a minimum of 25 mils of separation to other signals. Figure 37. Intel 855PM MCH HSWNG[1:0] Reference Voltage Generation Circuit +VCCP +VCCP 301Ω...

  • Page 73: Processor Fsb Strapping

    4.1.9. Processor FSB Strapping The Intel Pentium M processor / Intel Celeron M processor and Intel 855PM MCH both have pins that require termination for proper component operation. 1. For the processor, a stuffing option should be provided for the TEST[3:1] pins to allow a 1-k ±...

  • Page 74: Figure 39. Processor Strapping Resistor Layout

    The placement of the strapping resistors for TDI, TMS, TRST#, and TCK is not critical. Figure 39. Processor Strapping Resistor Layout SECONDARY SIDE TEST[2] A8, A17 & A20 TEST[1] Pins TRST# TEST[3] ® Intel 855PM Chipset Platform Design Guide...

  • Page 75: Figure 40. Vccsense /V

    A third ground via should also be placed in between them to allow for a differential probe ground. See Figure 40 for the recommended layout example. Figure 40. V Routing Example CCSENSE SSSENSE VCCSENSE 54.9 Ω 54.9 Ω 100mil VSSSENSE ® Intel 855PM Chipset Platform Design Guide...

  • Page 76: Intel System Validation Debug Support

    CPUs, chipsets, SIOs, PCI devices, and other hardware in a design. The ITP is widely used by validation, test, and debug groups within Intel (as well as by third party BIOS vendors, OEMs, and other developers).

  • Page 77: Implementation

    FSB Design Guidelines and debug groups within Intel (as well as by third party BIOS vendors, OEMs, and other developers). For the Intel Pentium M and Intel Celeron M processors, Agilent* Corporation will develop this tool and will likely be the only visibility to this critical system bus.

  • Page 78: Recommended Onboard Itp700Flex Implementation

    Figure 41 illustrates recommended connections between the onboard ITP700FLEX debug port, processor, Intel 855PM MCH, and CK-408 clock chip in the cases where the debug port is used. For the purpose of this discussion on ITP700FLEX signal routing, refer to Section 4.1.1.4 for more details on the signal propagation time to distance relationships for the length matching requirements listed as periods of time below.

  • Page 79: Figure 41. Itp700Flex Debug Port Signals

    1.05v 54.9 Ω 22.6 Ω TDOITP BPM[3:0]# BCLK[1:0] BPM[3:0]# BPM[5:0]# BPM[4]# PRDY# Intel BPM[5]# 240 Ω 240 Ω PREQ# 855PM 1.05v DBR# RESET# 54.9Ω RESET# DBA# CPURESET# RESETITP# RESET# 22.6 Ω DBR# DBA# ® Intel 855PM Chipset Platform Design Guide...
  • Page 80 BPM[5]#/PREQ# should not exceed 6.0 inches. As explained in Sections 4.1.5 and 4.1.5.1, the RESET# signal forks (see Figure 26) out from the Intel 855PM MCH’s CPURST# pin and is routed to the processor and ITP700FLEX debug port. One branch from the fork connects to the processor’s RESET# pin and the second branch connects to a 54.9...
  • Page 81 (1.05 V) plane with a 0.1-µF decoupling capacitor placed within 0.1 inch of the VTT pins. Table 17 summarizes termination resistors values, placement, and voltages the ITP signals need to connect to for proper operation for onboard ITP700FLEX debug port. ® Intel 855PM Chipset Platform Design Guide...

  • Page 82: Itp Signal Routing Example

    VTT and VTAP pins of the ITP700FLEX connector and also a transition back to the secondary side of the ® Intel 855PM Chipset Platform Design Guide...

  • Page 83: Itp_Clk Routing To Itp700Flex Connector

    ITP_CLK and the sum of length L6 of the BCLK[1:0] lines and the additional length L2 of the BPM#[5:0] signals in Figure 41. The ITP_CLK pair routing then switches back to the primary side layer through a via near the ITP700FLEX connector. ® Intel 855PM Chipset Platform Design Guide...

  • Page 84: Figure 42. Itp_Clk To Itp700Flex Connector Layout Example

    FSB Design Guidelines Figure 42. ITP_CLK to ITP700FLEX Connector Layout Example ITP700FLEX ITP700FLEX PRIMARY SIDE PRIMARY SIDE Connector Connector 49.9Ω 49.9Ω 33Ω 33Ω ITP_CLK ITP_CLK CK-408 CK-408 ITP_CLK ITP_CLK LAYER 6 LAYER 6 ITP_CLK# ITP_CLK# ® Intel 855PM Chipset Platform Design Guide...

  • Page 85: Itp700Flex Design Guidelines For Production Systems

    RESET# is not modified. RESET# would be a long, unterminated transmission line if the 54.9 ± 1% is not populated and could affect CPURST# signal quality and performance at the Intel 855PM MCH and the processor. If the routing for RESET# is removed or disconnected at the output of the MCH’s CPURST# pin, then it is possible to also remove the 54.9...

  • Page 86: Recommended Itp Interposer Debug Port Implementation

    4.3.2. Recommended ITP Interposer Debug Port Implementation Intel is working with American Arium* to provide ITP interposer cards for use in debugging Intel Pentium M and Intel Celeron M processor based systems as an alternative to the onboard ITP700FLEX in cases where the onboard connector cannot be supported. The ITP interposer card is an additional component that integrates a processor socket along with ITP700 connector on a single interposer card that is compatible with the 478-pin Intel Pentium M processor / Intel Celeron M processor socket.

  • Page 87: Itp Interposer Design Guidelines For Production Systems

    Specific information must be obtained from the logic analyzer vendor. Due to the complexity of an Intel Pentium M/Intel Celeron M processor-based system, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing an Intel Pentium M/Intel Celeron M processor-based system that can make use of an LAI: mechanical and electrical.

  • Page 88: Mechanical Considerations

    Intel 855PM MCH FSB Signal Package Lengths Table 18 lists the package trace lengths of the Intel Pentium M processor / Intel Celeron M processor and the Intel 855PM MCH for the source synchronous data and address signals. All the signals within the same group are routed to the same length as listed below with ±...

  • Page 89: Table 18. Processor And Mch Fsb Signal Package Trace Lengths

    HDSTBP[3]# DSTBN[3]# H DSTBN[3]# REQ[4:0]# HREQ[4:0]# Address A[16:3]# HA[16:3]# Group 1 ADSTB[0]# HADSTB[0]# A[31:17]# HA[31:17]# Address Group 2 ADSTB[1]# HADSTB[1]# COMMON CLOCK SIGNALS ADS# ADS# BNR# BNR# BPRI# BPRI# BR0# BREQ0# DBSY# DBSY# ® Intel 855PM Chipset Platform Design Guide...
  • Page 90 Trace Length (mils) DEFER# DEFER# DPWR# DPWR# DRDY# DRDY# HIT# HIT# HITM# HITM# LOCK# HLOCK# RS[0]# RS[0]# RS[1]# RS[1]# RS[2]# RS[2]# TRDY# HTRDY# RESET# CPURST# DIFFERENTIAL HOST CLOCKS BCLK0 BCLK0 Host Clocks BCLK1 BCLK1 ® Intel 855PM Chipset Platform Design Guide...

  • Page 91: Platform Power Requirements

    The Intel Celeron M processor does not support Enhanced Intel SpeedStep technology.

  • Page 92: Intel 855Pm Mch Pll Voltage Supply Power Sequencing

    Figure 45. The Layer 1 dog bone connection (not shown in Figure 45) should have a width of 25 mils for each of the VCCGA and VCCHA pins. Figure 45. Intel 855PM MCH 1.8 V V and V Recommended Power Delivery...
  • Page 93 Figure 46 illustrates the recommended layout example of the VCCA[3:0] pins feed and decoupling. The 1.8-V flood on Layer 3 from Intel 855PM MCH is via’ed up to the primary side layer with a cluster of five 1.8-V vias and two GND stitching vias as shown on the left and middle side of Figure 46. On the primary layer side, a wide flood in a “U-Shape”...

  • Page 94: Processor Pll Voltage Supply Power Sequencing

    5.3.2.1. Voltage Identification for Intel Pentium M/Intel Celeron M Processor There are six voltage identification pins on the Intel Pentium M/Intel Celeron M processor. These signals can be used to support automatic selection of V voltages. They are needed to cleanly CC-CORE support voltage specification variations on current and future processors.

  • Page 95: Figure 47. Intel® Pentium® M Processor / Intel® Celeron® M Processor Vid[5:0] Escape Routing Layout Example

    Platform Power Requirements Figure 47. Intel® Pentium® M Processor / Intel® Celeron® M Processor VID[5:0] Escape Routing Layout Example TO VRM TO VRM LAYER 3 LAYER 3 LAYER 6 LAYER 6 Secondary Secondary VID4 VID4 VID2 VID2 Side Side VID0...

  • Page 96: Table 19. Vid Vs. V

    0.956 1.452 0.940 1.436 0.924 1.420 0.908 1.404 0.892 1.388 0.876 1.372 0.860 1.356 0.844 1.340 0.828 1.324 0.812 1.308 0.796 1.292 0.780 1.276 0.764 1.260 0.748 1.244 0.732 1.228 0.716 1.212 0.700 ® Intel 855PM Chipset Platform Design Guide...

  • Page 97: Vccp Output Requirements

    FSB rail for the Intel Pentium M/Intel Celeron M processor, the Intel 855PM MCH, the 82801DBM ICH4-M, and ITP700FLEX debug port if it is used. For the ICH4-M, this rail is known as V The voltage regulator can be programmed via an external CPU_IO.

  • Page 98: Vcc-Mch Output Requirements

    5.5. Output Requirements CC-MCH The V output rail provides power to the core of the Intel 855PM MCH. The nominal voltage of CC-MCH is 1.2 V. The voltage regulator can be programmed via an external resistor network. See Figure CC-MCH 50.
  • Page 99 This can also decrease the cost and PCB area needed for the total solution. The implementation options for this topology are discussed in the next section. ® Intel 855PM Chipset Platform Design Guide...

  • Page 100: Voltage Regulator Topology

    DRIVER STAGE STAGE 5.8. Voltage Regulator Design Recommendations When laying out the processor power delivery circuit using a traditional Buck Voltage Regulator on a printed circuit board, the following checklist should be followed. ® Intel 855PM Chipset Platform Design Guide...

  • Page 101: High Current Path, Top Mosfet Turned On

    These high-density points are located along the shortest route between the processor core and the sense resistor. Using short, fat traces or planes can minimize both stray inductance and resistance. ® Intel 855PM Chipset Platform Design Guide...

  • Page 102: High Current Paths During Switching Dead Time

    Schottky diode to the bottom MOSFET(s), the current path shown by the dashed/arrow line in Figure 56. Minimize stray inductance and resistance with short, fat traces or planes. ® Intel 855PM Chipset Platform Design Guide...

  • Page 103: General Layout Recommendations

    (20 to 25 mils). Ideally, the driver has to be placed right next to the MOSFETs. Circuits using multiple top or bottom MOSFETs need to have the gate traces serpentined so the all ® Intel 855PM Chipset Platform Design Guide...

  • Page 104: Processor Decoupling Recommendations

    5.9. Processor Decoupling Recommendations Intel recommends proper design and layout of the system board bulk and high frequency decoupling capacitor solution to meet the transient tolerance at the processor package balls. To meet the transient response of the processor, it is necessary to properly place bulk and high frequency capacitors close to the processor power and ground pins.

  • Page 105: High Frequency, Mid Frequency, And Bulk Decoupling

    25 A. It should be noted CCMAX that current consumption of Intel Pentium M processor and Intel Celeron products may be lower than what is shown in Figure 57. However, to guarantee the suitability of the motherboard and VRM design...

  • Page 106: Processor Core Voltage Plane And Decoupling

    CORE external power planes. Sharing of vias between several V pins or ground pins is not allowed. CC-CORE ® Intel 855PM Chipset Platform Design Guide...

  • Page 107: Figure 58. Intel Pentium M Processor And Intel Celeron M Processorsocket Core Power Delivery Corridor

    Platform Power Requirements Figure 58. Intel Pentium M Processor and Intel Celeron M ProcessorSocket Core Power Delivery Corridor VR Feed VR Feed 49 VCC/GND 49 VCC/GND Pairs Pairs 24 VCC/GND 24 VCC/GND Pairs Pairs A conceptual diagram of this V power delivery scheme is shown in Figure 59.

  • Page 108: Figure 59. Processor Core Power Delivery And Decoupling Concept

    ~1.2 nH ESL for 1206 form factor capacitors. Please note that the 0805 capacitors have and ground vias on both negative and positive terminals similar to the 220- F SP capacitors in CC-CORE order to achieve a low inductance connection. ® Intel 855PM Chipset Platform Design Guide...

  • Page 109: Table 20. Vcc-Core Decoupling Guidelines 1

    Only three of the mid- frequency decoupling capacitors need to be placed on the primary side. Table 20 lists the decoupling solutions recommended by Intel for the processor’s V voltage rail.
  • Page 110 To allow good current flow from the SP capacitors to the north side of the V CC-CORE corridor pins, Intel recommends that these eight, 10- F 0805 capacitors be spaced 100 mils apart from each other even if the motherboard design rules allow tighter spacing. The 100-mil horizontal spacing...
  • Page 111 In terms of robustness, this refers to creating a low resistance and inductance connection between the bulk and mid frequency capacitors and the processor pins. ® Intel 855PM Chipset Platform Design Guide...

  • Page 112: Figure 60. Vcc-Core Power Delivery And Decoupling Example - (Primary And Secondary Side Layers)

    Figure 61. Processor Core Power Delivery “North Corridor” Zoom In View 4x220uF SP Cap 4x220uF SP Cap Primary Side Primary Side Sense Resistors Sense Resistors Secondary Side Secondary Side VR feed VR feed 90mil 90mil 90mil 90mil 100mil 100mil 90mil 90mil ® Intel 855PM Chipset Platform Design Guide...

  • Page 113: Figure 62. Vcc-Core Power Delivery And Decoupling Example (Layers 3, 5, And 6)

    Figure 63. Recommended SP Cap Via Connection Layout (Secondary Side Layer) 50 mils 50 mils 82 mils 82 mils 50 mils 50 mils 82 mils 82 mils 220 mils 220 mils VCC-CORE VCC-CORE ® Intel 855PM Chipset Platform Design Guide...

  • Page 114: Intel Pentium M Processor / Intel Celeron M Processor And Intel 855Pm Mch

    Intel 855PM MCH V Voltage Plane and Decoupling The 400-MHz high frequency operation of the Intel Pentium M/Intel Celeron M and Intel 855PM MCH’s FSB requires careful attention to the design of the power delivery for V (1.05 V) to the processor and MCH.
  • Page 115 MCH and circumvents the 1.5-V and 1.8-V plane floods to the MCH by routing around the AGP bus signal quadrant (not shown in figures). Refer to Figure 65 for more details. ® Intel 855PM Chipset Platform Design Guide...

  • Page 116: Figure 64. Processor V Power Delivery And Decoupling Concept

    VCCP = 1.05v VCCP = 1.05v 150uF POSCAP 150uF POSCAP 150uF POSCAP 150uF POSCAP Short DATA & ADDR Short DATA & ADDR Short DATA & ADDR Short DATA & ADDR Sides Sides Sides Sides ® Intel 855PM Chipset Platform Design Guide...
  • Page 117 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 10x0.1uF 0603 ® Intel 855PM Chipset Platform Design Guide...

  • Page 118: Ccp

    Intel 855PM MCH V Voltage Plane and Decoupling The Intel 855PM MCH conceptual V (1.05 V) power delivery cross section is illustrated in Figure 66. Similar to the concept for the processor, the secondary side layer (Layer 8) that references the solid ground plane on Layer 7 located 4 mils above (see Figure 2) creates a low inductance short between the 150-µF POSCAPs and the 0.1 µF 0603 form factor capacitors placed inside and outside of the package...

  • Page 119: Intel 855Pm Mch Core Voltage Plane And Decoupling

    The left side of Figure 67 illustrates how the conceptual cross section (right side of Figure 67) of the (1.05 V) plane for power delivery for the Intel 855PM MCH translates into an actual layout. The entire section of the MCH pin-map related to the FSB signals is a flood with a V plane on the secondary side (Layer 8).

  • Page 120: Table 22. Vcc-Mch Decoupling Guidelines

    CC-MCH Notice the orientation of the dog bones on the primary side layer (Layer 1) since this is critical to fit all the required components on the secondary side. ® Intel 855PM Chipset Platform Design Guide...
  • Page 121 The top right side of Figure 70 shows how most of Layer 5 under the Intel 855PM MCH package outline shadow is a ground plane except for a narrow corridor that allows for the escape routing of the out of the pin field.

  • Page 122: Figure 70. V Power Planes And Decoupling Example

    Figure 70. V Power Planes and Decoupling Example CC-MCH VR Feed Primary Side Layer 5 1.2v for PSB Signals 1.2v 2x150uF VR Feed 1.05v Secondary Layer 6 1.2v Side 1.5v 1.8v 1.2v 2.5v ® Intel 855PM Chipset Platform Design Guide...

  • Page 123: Figure 71. V Secondary Layer Decoupling Capacitor Placement (Zoom In View)

    Secondary Layer Decoupling Capacitor Placement (Zoom in View) CC-MCH 25mil 1.05v Secondary Side 25mil 2x150µF 0805 2.2µF Extra Via 1.5v 1.2v Extra Via 0603 45mil 1.8v 22nF 45mil 0603 0603 0603 0603 10nF 47nF 15nF 220nF 2.5v ® Intel 855PM Chipset Platform Design Guide...
  • Page 124 Platform Power Requirements This page intentionally left blank. ® Intel 855PM Chipset Platform Design Guide...

  • Page 125: System Memory Design Guidelines (Ddr-Sdram)

    System Memory Design Guidelines (DDR-SDRAM) The Intel 855PM chipset Double Data Rate (DDR) SDRAM system memory interface consists of 121 CMOS signals. These CMOS signals have been divided into several signal groups: Data, Command, Control, Feedback, and Clock signals. Table 23 summarizes the different signal grouping. Refer to the ®...

  • Page 126: Ddr 200/266/333 Mhz System Memory Topology And Layout Design Guidelines

    The simulated motherboard r was 3.8 and 4.5. Note: Intel has conducted simulations for 2x8 SO-DIMMs that are based on the 1x8 raw card B populated with Dual Die Package (DDP) SDRAM parts based on 512-Mbit devices (two 256-Mbit dies within the same package).

  • Page 127: Figure 72. Data Signal Routing Topology

    Min = 0.5” Trace Length L1 – MCH Signal Ball to Series Figure 74 3, 5 Termination Resistor Pad Max = 3.75” Max = 0.75” Figure 74 Trace Length L2 – Series Termination Resistor ® Intel 855PM Chipset Platform Design Guide...
  • Page 128 SO-DIMM Pad Trace Length L4 – Last SO-DIMM Pad to Parallel Max = 0.80” Figure 74 Termination Resistor Pad Overall routing length from 855PM MCH to last Min = 0.5” SO-DIMM Pad– L1+Rs+L2+L3 (required for Max= 4.5” DDR333 support) Series Termination Resistor (Rs) ±...

  • Page 129: Data To Strobe Length Matching Requirements

    ± 25 mils SDQS7 SDQ[71:64] ± 25 mils SDQS8 Note: The recommended individual trace lengths (i.e. L1, L2, and L3) specifications can not be violated when the signal lengths are tolerance by ± 25 mils. ® Intel 855PM Chipset Platform Design Guide...

  • Page 130: Figure 73. Dq/Cb To Dqs Trace Length Matching Requirements

    DQ/CB Length (Y) = DQ/CB[2] (X ±25 mils) DQ/CB[3] DQS Length = X DQ/CB[4] DQ/CB[5] DQ/CB Length (Y) = DQ/CB[6] (X ±25 mils) DQ/CB[7] Note: Lengths are measured from MCH-M pin to SO-DIMM1 connector pads. ® Intel 855PM Chipset Platform Design Guide...

  • Page 131: Strobe To Clock Length Matching Requirements

    1.025 inches to and 2.475 inches. If the CLK to one SO-DIMM is all equal in length, 2.00 inches for example then the strobes (DQS) can be routed between 1.00 inches to 2.50 inches. Refer to Section 4.4 for package trace length data. ® Intel 855PM Chipset Platform Design Guide...

  • Page 132: Figure 74. Sdqs To Sck/Sck# Trace Length Matching Requirements

    DQS Length = Y ( Y - 0.5" ) < = X < = ( Y + 1.0" ) SCK[5:3] SCK/SCK#[5:3] Length = X SCK#[5:3] Note: Lengths are measured from MCH-M pad to SO-DIMM1 connector pads. ® Intel 855PM Chipset Platform Design Guide...

  • Page 133: Data Routing Example

    From Intel 855PM MCH From Intel 855PM MCH-M From Intel 855PM MCH-M From Intel 855PM MCH-M From Intel 855PM MCH-M From Odem From Odem From Odem From Odem Data Signals Data Signals Data Signals Data Signals ® Intel 855PM Chipset Platform Design Guide...

  • Page 134: Support For Small Form Factor Design Ddr Data Bus Routing

    Support for Small Form Factor Design DDR Data Bus Routing The layout and routing guidelines for the system memory interface of the Intel 855PM MCH have been optimized to address the requirements of small form factor designs (i.e., mini-note, sub-note, and tablet PCs).

  • Page 135: Figure 76. Control Signal Routing Topology

    The overall maximum and minimum length to the SO-DIMM must comply with clock length matching requirements. L1 trace length does not include MCH package length and should not be used when calculating L1 length. ® Intel 855PM Chipset Platform Design Guide...

  • Page 136: Control To Clock Length Matching Requirements

    SO-DIMM1 must be between 4.0 inches to 5.5 inches. Figure 77 depicts the length matching requirements between the control and clock signals. The MCH package lengths do not need to be taken into account for routing length matching purposes. ® Intel 855PM Chipset Platform Design Guide...

  • Page 137: Figure 77. Control Signal To Sck/Sck# Trace Length Matching Requirements

    ( Y - 1.0" ) < = X < = ( Y + 0.5" ) SCK[5:3] SCK/SCK#[5:3] Length = X SCK#[5:3] Note: Lengths are measured from MCH-M pins to SO- DIMM1 connector pads. ® Intel 855PM Chipset Platform Design Guide...

  • Page 138: Control Routing Example

    From Intel 855PM MCH-M From Intel 855PM MCH From Intel 855PM MCH From Odem From Odem From Odem From Odem Signals Signals Signals Signals To Parallel To Parallel To Parallel To Parallel Termination Termination Termination Termination ® Intel 855PM Chipset Platform Design Guide...

  • Page 139: Command Signals - Sma[12:0], Sbs[1:0], Sras#, Scas#, Swe

    6.1.3.1.1. Routing Description for Command Topology 1 The command signal group routing starting from Intel 855PM MCH is as follows. The command signal routing should transition immediately from an external layer to an internal signal layer under the MCH. Keep to the same internal layer until transitioning back to an external layer immediately prior to connecting the SO-DIMM0 connector pad.

  • Page 140: Table 28. Command Topology 1 Routing Guidelines

    It is possible to route using 4 vias if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. L1 trace length does not include MCH package length and should not be used when calculating L1 length. ® Intel 855PM Chipset Platform Design Guide...

  • Page 141: Command Topology 1 To Clock Length Matching Requirements

    SO-DIMM1 must be between 5.0 inches to 6.5 inches. Figure 80 depicts the length matching requirements between the command and clock signals. The MCH package lengths do not need to be taken into account for routing length matching purposes. ® Intel 855PM Chipset Platform Design Guide...

  • Page 142: Figure 80. Command Signal To Sck/Sck# Trace Length Matching Requirements

    ( Y - 1.0" ) < = X < = ( Y + 0.5" ) SCK[5:3] SCK/SCK#[5:3] Length = X SCK#[5:3] Note: CMD Lengths are measured from MCH-M pins to SO-DIMM1 connector pads. ® Intel 855PM Chipset Platform Design Guide...

  • Page 143: Command Topology 1 Routing Example

    Figure 81. Command Signals Topology 1 Routing Example From Intel From Odem 855PM MCH Series Dampening Series Dampening Resistor Rs Resistor Rs Parallel Termination Parallel Termination on Both Layers on Both Layers ® Intel 855PM Chipset Platform Design Guide...

  • Page 144: Command Topology 2 Solution

    6.1.3.2.1. Routing Description for Command Topology 2 The command signal group routing starting from Intel 855PM MCH is as follows. The command signal routing should transition immediately from an external layer to an internal signal layer under the MCH. Keep to the same internal layer until transitioning back to an external layer at the series resistor Rs. At this point there is a T in the topology.

  • Page 145: Table 29. Command Topology 2 Routing Guidelines

    It is possible to route using 3 vias if one via is shared that connects L1, L3, and series termination and if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. L1 trace length does not include MCH package length and should not be used when calculating L1 length. ® Intel 855PM Chipset Platform Design Guide...

  • Page 146: Command Topology 2 To Clock Length Matching Requirements

    SO-DIMM1 must be between 5.0 inches to 6.5 inches. Figure 83 depicts the length matching requirements between the command and clock signals. The MCH package lengths do not need to be taken into account for routing length matching purposes. ® Intel 855PM Chipset Platform Design Guide...

  • Page 147: Figure 83. Command Signal To Sck/Sck# Trace Length Matching Requirements

    ( Y - 1.0" ) < = X < = ( Y + 0.5" ) SCK[5:3] SCK/SCK#[5:3] Length = X SCK#[5:3] Note: CMD Lengths are measured from MCH-M pins to SO-DIMM1 connector pads. ® Intel 855PM Chipset Platform Design Guide...

  • Page 148: Command Topology 2 Routing Example

    SO-DIMMs) the SO-DIMMs) the SO-DIMMs) the SO-DIMMs) Could be RPacks Could be RPacks Could be RPacks Could be RPacks ® Intel 855PM Chipset Platform Design Guide...

  • Page 149: Clock Signals - Sck[5:0], Sck#[5:0]

    6.1.4. Clock Signals – SCK[5:0], SCK#[5:0] The clock signal group includes the differential clock pairs SCK[5:0] and SCK#[5:0]. The Intel 855PM MCH generates and drives these differential clock signals required by the DDR interface; therefore, no external clock driver is required for the DDR interface. The MCH only supports unbuffered DDR SO- DIMMs, three differential clock pairs are routed to each SO-DIMM connector.

  • Page 150: Table 31. Clock Signal Group Routing Guidelines

    Simulations show improved timing margin resulting from use of a 7-mil clock trace width. Option 1 OR Option 2 must be implemented for all SCK/SCK# pairs for a given design. The two options should not be combined within one design. ® Intel 855PM Chipset Platform Design Guide...

  • Page 151: Clock Signal Length Matching Requirements

    6.1.4.1. Clock Signal Length Matching Requirements The Intel 855PM MCH provides three differential clock pair signals for each SO-DIMM. A differential clock pair is made up of a SCK signal and its complement signal SCK#. The differential pairs for one SO-DIMM are:...

  • Page 152: Figure 86. Sck/Sck# Trace Length Matching Requirements

    SCK#4 Length = Y SCK#4 | <= 0.01 inches SCK5 SCK5 Length = Y SCK#5 SCK#5 Length = Y | <= 0.01 inches Note: Lengths are measured from MCH-M pin to SO- DIMM1 connector pads. ® Intel 855PM Chipset Platform Design Guide...

  • Page 153: Figure 87. Clock Pair Trace Length Matching Requirements

    Max (Y ) - Min (Y ) <= 0.025 inches Note: Lengths are measured from MCH-M pin to SO-DIMM1 connector pads NOTE: Length matching between DQS and Clock pairs must include package length. ® Intel 855PM Chipset Platform Design Guide...

  • Page 154: Clock Routing Example

    Figure 88. Clock Signal Routing Example Intel 855PM Intel 855PM Intel 855PM Intel 855PM Intel 855PM Intel 855PM Odem Odem Odem Odem MCH-M MCH-M MCH-M MCH-M Clocks Clocks Clocks Clocks SO-DIMM0 SO-DIMM0 SO-DIMM0 SO-DIMM0 SO-DIMM1 SO-DIMM1 SO-DIMM1 SO-DIMM1 ® Intel 855PM Chipset Platform Design Guide...

  • Page 155: Intel 855Pm Chipset High Density Memory Support

    Feedback – RCVENOUT#, RCVENIN# The Intel 855PM MCH provides a feedback signal called “receive enable” (RCVEN#), which is used to gate the strobe inputs for read data. There are two pins on the MCH to facilitate the use of RCVEN#.

  • Page 156: Rcven# Routing Example

    L3 trace length does not include MCH package length and should not be used when calculating L3 length. 6.1.5.1. RCVEN# Routing Example Figure 90 is an example of a board routing implementation for the RCVEN# signal. Clock routing is show in red. ® Intel 855PM Chipset Platform Design Guide...

  • Page 157: Support For "Ddp Stacked" So-Dimm Modules

    512-Mbit technology-based (two 256-Mbit dies within the same package), “DDP stacked”, 2x8 SO-DIMM memory modules on Intel 855PM chipset based platforms. For the purpose of this discussion, the term “DDP stacked” is used to refer to DDP SDRAM based 2x8 SO-DIMM memory modules.

  • Page 158: Recommended Design Option To Support Pc2700 Ddr Sdram With Existing Pc1600 And Pc2100 Intel 855Pm Platforms

    System Memory Design Guidelines (DDR-SDRAM) 6.1.7. Recommended Design Option to Support PC2700 DDR SDRAM with Existing PC1600 and PC2100 Intel 855PM Platforms The following sections document the currently available design option for enabling PC2700 DDR SDRAM support based on existing platform layouts.

  • Page 159: Additional Design Considerations For Adapting Intel 855Pm Ddr 200/266 Mhz Platforms To Support Pc2700

    System Memory Design Guidelines (DDR-SDRAM) 6.1.7.1.2. Additional Design Considerations for Adapting Intel 855PM DDR 200/266 MHz Platforms To Support PC2700 In addition to meeting the updated routing length requirements specified in Section 6.2.7.1, future DDR 333-MHz platforms must also adhere to all other existing design guidelines for the DDR 200-MHz and 266-MHz platforms.

  • Page 160: Intel 855Pm Mch Ddr Signal Package Lengths

    0.1 mils inside the package. Thus, motherboard routing does not need to compensate for trace length mismatch in the package for these signals. Table 35. Intel 855PM Chipset DDR Signal Package Lengths Intel 855PM MCH Package...

  • Page 161: Ddr System Memory Interface Strapping

    6.4. ECC Disable Guidelines The Intel 855PM MCH can be configured to operate in an ECC data integrity mode that allows for multiple bit error detection and single bit error correction. This option to design for and support ECC DDR memory modules is dependent on design objectives. By default, ECC functionality is disabled on the platform.

  • Page 162: Ddr Memory Ecc Functionality Disable

    CS/CKE and SCK signals to unpopulated SO-DIMMs. Although DDR SO- DIMM connectors may provide motherboard lands for three clock pairs, Intel design recommendations only support non-ECC SO-DIMMs that require two pairs. The MCH provides the flexibility to route any differential clock pair to any SCK clock pair on the SO-DIMMs provided that the BIOS enables/disables these clocks appropriately (e.g.

  • Page 163: External Thermal Sensor Based Throttling (Ets#)

    External Thermal Sensor Based Throttling (ETS#) The Intel 855PM MCH’s ETS# input pin is an active low input that can be used with an external thermal sensor to monitor the temperature of the DDR SO-DIMMs for a possible thermal condition. Assertion of ETS# will result in the limiting of DRAM bandwidth on the DDR memory interface to reduce the temperature in the vicinity of the system memory.

  • Page 164: Ets# Design Guidelines

    ETS# Design Guidelines ETS#, as implemented in the Intel 855PM MCH, is an active low signal and does not have an integrated pull-up to maintain a logic ‘1’. As a result of this, a placeholder for an external 8.2-k to 10-k pull-up resistor should be provided near the ETS# pin.

  • Page 165: Figure 92. Ddr Memory Thermal Sensor Placement

    Sensor location within approx 15mm of Sensor location within approx 15mm of SO-DIMM outline will not be as SO-DIMM outline will not be as effective at controlling fast transient effective at controlling fast transient temperature changes temperature changes ® Intel 855PM Chipset Platform Design Guide...
  • Page 166 System Memory Design Guidelines (DDR-SDRAM) This page intentionally left blank. ® Intel 855PM Chipset Platform Design Guide...

  • Page 167: Agp Port Design Guidelines

    A single AGP controller is supported by the Intel 855PM MCH AGP interface. LOCK# and SERR#/PERR# are not supported. The AGP buffers operate in only one mode: AGP 4X, 2X and 1X operate at 1.5 V only.

  • Page 168: Agp 2.0 Spec

    RBF# WBF# ST[2:0] PIPE# REQ# GNT# FRAME# IRDY# TRDY# STOP# DEVSEL# 2X / 4X timing domain Set #1 AD[15:0] C/BE[1:0]# AD_STB0 AD_STB0# Set #2 AD[31:16] C/BE[3:2]# AD_STB1 AD_STB1# Set #3 SBA[7:0] SB_STB SB_STB# ® Intel 855PM Chipset Platform Design Guide...

  • Page 169: Agp Routing Guidelines

    36. In addition to this maximum trace length requirement (refer to Table 38 and Table 39) these signals must meet the trace spacing and trace length mismatch requirements in Sections 7.3.1.2 and 7.3.1.3. ® Intel 855PM Chipset Platform Design Guide...

  • Page 170: Trace Spacing Requirements

    (trace spacing) and line lengths. These routing rules are divided by trace spacing. In 1:2 spacing, the distance between the traces is two times the width of traces. Simulations in a mobile environment support this rule. ® Intel 855PM Chipset Platform Design Guide...

  • Page 171: Trace Spacing Requirements

    ± 0.1 inches. This is for designs that require less than 6 inches between the graphics device and the Intel 855PM MCH. See Figure 93 for details. Reduce line length mismatch to ensure added margin. In order to reduce trace to trace coupling (cross talk), separate the traces as much as possible.

  • Page 172: Trace Length Mismatch Requirements

    Trace length mismatch for all signals within a signal group should be as close to 0 inches as possible to provide optimal timing margin. Table 41 shows the AGP 2.0 routing summary. ® Intel 855PM Chipset Platform Design Guide...

  • Page 173: Agp Clock Skew

    7.3.3. AGP Clock Skew The maximum total AGP clock skew, between the Intel 855PM MCH and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter, which originates on the motherboard, add-in module (if used), and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but also at all points on the clock edge that falls in the switching range.

  • Page 174: Agp Routing Ground Reference

    AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_TRDY#, G_IRDY#, G_GNT#, and ST[2:0]. In addition to the minimum signal set listed previously, Intel strongly recommends that half of all AGP signals be referenced to ground, depending on the board layout. In an ideal design, the complete AGP interface signal field would be referenced to ground.

  • Page 175: Table 42. Agp Pull-Up/Pull-Down Requirements And Straps

    1, 6 NOTES: The Intel 855PM MCH has integrated pull-ups to ensure that these signal do not float when there is no add-in card in the connector. The Intel 855PM MCH does not implement the PERR# and SERR# signals. Pull-ups on the motherboard are required for AGP graphics controllers that implement these signals.

  • Page 176: Agp Vddq And Vref

    7.3.8.1. 1.5-V AGP Interface (2X/4X) In order to account for potential differences between VDDQ and GND at the Intel 855PM MCH and graphics controller, both devices use source generated Vref . That is, the Vref signal is generated at the graphics controller and sent to the MCH and another Vref is generated at the MCH and sent to the graphics controller.

  • Page 177: Hub Interface

    Synthesizer 8.1. Hub Interface Compensation This hub interface connects the 82801DBM ICH4-M and the Intel 855PM MCH. The hub interface uses a compensation signal to adjust buffer characteristics to the specific board characteristic. The hub interface requires resistive compensation (RCOMP).

  • Page 178: Internal Layer Routing

    Traces should be routed 4 mils wide with 8 mils trace spacing (4 on 8) and 20 mils spacing from other signals. In order to break out of the Intel 855PM MCH and Intel 82801DBM ICH4-M packages, the HI[7:0] signals can be routed 4 on 4. The signal must be separated to 4 on 8 within 300 mils from the package.

  • Page 179: Hub Interface Data Hi[10:8] Signals

    8.3.3. Terminating HI[11] The HI[11] signal exists on the Intel 82801DBM ICH4-M but not the Intel 855PM MCH and is not used on the platform. It can be left as a no connect. 8.4. HIREF/HI_VSWING Generation/Distribution HIREF is the hub interface reference voltage used on both the Intel 855PM MCH and the Intel 82801DBM ICH4-M.

  • Page 180: Figure 95. Hub Interface With Single Reference Voltage Divider Circuit

    Figure 95. Hub Interface with Single Reference Voltage Divider Circuit HI=1.8V Intel Intel 855PM ICH4-M HIREF HIREF HI_VSWING Figure 96. Hub Interface with Locally Generated Reference Voltage Divider Circuit HI=1.8V HI_VSWING HIREF Intel ICH4-M ® Intel 855PM Chipset Platform Design Guide...

  • Page 181: Hub Interface Decoupling Guidelines

    The main focus of these guidelines is to minimize signal integrity problems on the hub interface of the Intel 855PM MCH. To improve I/O power delivery, use two 0.1-µF capacitors per each component (i.e. the ICH4-M and MCH). These capacitors should be placed within 150 mils from each package, adjacent to the rows that contain the hub interface.
  • Page 182 Hub Interface This page intentionally left blank. ® Intel 855PM Chipset Platform Design Guide...

  • Page 183: I/O Subsystem

    Grounding: Provide a direct low impedance chassis path between the motherboard ground and hard disk drives. Intel 82801DBM ICH4-M Placement: The ICH4-M must be placed equal to or less than 8 inches from the ATA connector(s). ®...

  • Page 184: Primary Ide Connector Requirements

    The 10-k resistor to ground on the PDIAG#/CBLID# signal is required on the Primary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® Intel 855PM Chipset Platform Design Guide...

  • Page 185: Secondary Ide Connector Requirements

    The 10-k resistor to ground on the PDIAG#/CBLID# signal is required on the Secondary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® Intel 855PM Chipset Platform Design Guide...

  • Page 186: Mobile Ide Swap Bay Support

    9.1.4. Mobile IDE Swap Bay Support Systems that require the support for an IDE “hot” swap drive bay can be designed to utilize the Intel 82801DBM ICH4-M’s IDE interface disable feature to achieve this functionality. To support a mobile “hot” swap bay, the ICH4-M allows the IDE output signals to be tri-stated or driven low and input buffers to be turned off.

  • Page 187: S5/G3 To S0 Boot Up Procedures For Ide Swap Bay

    2. The IORDY Sample Point Enable bit of the IDE_TIM register for the appropriate IDE device should then be set to ‘1’ to enable IORDY sampling by the Intel 82801DBM ICH4-M. This allows the OS to access the IDE device once again and waits for the assertion of IORDY in response to an access request.

  • Page 188: Pci

    I/O Subsystem 9.2. The Intel 82801DBM ICH4-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2.2. The implementation is optimized for high performance data streaming when the ICH4-M is acting as either the target or the initiator in the PCI bus.

  • Page 189: Figure 100. Intel 82801Dbm Ich4-M Ac'97 - Codec Connection

    I/O Subsystem Figure 100. Intel 82801DBM ICH4-M AC’97 – Codec Connection AC / MC / AMC RESET# SDATA_OUT SYNC Intel Primary BIT_CLK ICH4-M Codec SDATA_IN0 SDATA_IN1 SDATA_IN2 AC / MC / AMC Secondary Codec AC / MC / AMC Tertiary...

  • Page 190: Figure 101. Intel 82801Dbm Ich4-M Ac'97 - Ac_Bit_Clk Topology

    I/O Subsystem AC_SDIN1, and AC_SDIN2 may not be driven. If the link is enabled, the assumption can be made that there is at least one codec. Figure 101. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology Intel ICH4-M AC_BIT_CLK Primary Codec Table 48.

  • Page 191: Figure 103. Intel 82801Dbm Ich4-M Ac'97 - Ac_Sdin Topology

    Results showed that if the AD1885 codec was used a 33- resistor was best for R1 and if the CS4205b codec was used a 47- resistor for R1 was best. Bench data shows that a 47- resistor for R1 is best for the Sigmatel* 9750 codec. Figure 103. Intel 82801DBM ICH4-M AC’97 – AC_SDIN Topology Codec Intel...

  • Page 192: Ac'97 Routing

    Regions between digital signal traces should be filled with copper, which should be electrically attached to the digital ground plane. Locate the crystal or oscillator close to the codec. ® Intel 855PM Chipset Platform Design Guide...

  • Page 193: Motherboard Implementation

    9.3.2. Motherboard Implementation The following design considerations are provided for the implementation of an Intel 82801DBM ICH4- M platform using AC’97. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues. These recommendations are not the only implementation or a complete checklist, but they are based on the ICH4-M platform.

  • Page 194: Usb 2.0 Guidelines And Recommendations

    Route all traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing over anti-etch if at all possible. Crossing over anti-etch (plane splits) increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with USB 2.0 ® Intel 855PM Chipset Platform Design Guide...

  • Page 195: Usb 2.0 Trace Separation

    The USBRBIAS pin and the USBRBIAS# pin can be shorted and routed 5 on 5 to one end of a 22.6 ±1% resistor to ground. Place the resistor within 500 mils of the Intel 82801DBM ICH4-M and avoid routing next to clock pins.

  • Page 196: Usb 2.0 Termination

    All lengths are based upon using a common-mode choke (see Section 9.4.4.1 for details on common-mode choke). 9.4.2. Plane Splits, Voids, and Cut-Outs (Anti-Etch) The following guidelines apply to the use of plane splits voids and cutouts. ® Intel 855PM Chipset Platform Design Guide...

  • Page 197: Vcc Plane Splits, Voids, And Cut-Outs (Anti-Etch)

    If the system fuse is rated at 1amps then the power carrying traces should be wide enough to carry at least 1.5 amps. ® Intel 855PM Chipset Platform Design Guide...

  • Page 198: Emi Considerations

    Common mode chokes with a target impedance of 80 to 90 at 100 MHz generally provide adequate noise attenuation. ® Intel 855PM Chipset Platform Design Guide...

  • Page 199: Esd

    Figure 108. Other types of low-capacitance ESD protection devices may work as well but were not investigated. As with the common mode choke solution, Intel recommends including footprints for some type of ESD protection device as a stuffing option in case it is needed to pass ESD testing.

  • Page 200: Smbus 2.0/Smlink Interface

    I/O Subsystem The Intel® Pentium® M Processor / Intel® Celeron® M Processor does not have pins dedicated for a serial I/O APIC bus interface and thus, no hardware change is necessary. However, it is strongly encouraged to enable I/O APIC support in the BIOS and operating system on the processor based systems rather than the legacy 8259 interrupt controller due to the performance benefits and efficiencies that the I/O (x) APIC architecture enjoys over the older PIC architecture.

  • Page 201: Smbus Architecture And Design Considerations

    Controller SMbus-SMlink_IF Note: Intel does not support external access of the ICH4-M’s Integrated LAN Controller via the SMLink interface. Also, Intel does not support access of the ICH4-M’s SMBus Slave Interface by the ICH4-M’s SMBus Host Controller. Refer to the Intel ®...

  • Page 202: General Design Issues/Notes

    2. The maximum bus capacitance that a physical segment can reach is 400 pF. 3. The Intel ICH4-M does not run SMBus cycles while in S3. 4. SMBus devices that can operate in S3 must be powered by the V supply.

  • Page 203: Table 54. Bus Capacitance Reference Chart

    0 to 100 pF 8.2 k to 1.2 k 100 to 200 pF 4.7 k to 1.2 k 200 to 300 pF 3.3 k to 1.2 k 300 to 400 pF 2.2 k to 1.2 k ® Intel 855PM Chipset Platform Design Guide...

  • Page 204: Fwh

    I/O Subsystem 9.7. The following provides general guidelines for compatibility and design recommendations for supporting the FWH device. The majority of the changes will be incorporated in the BIOS. Refer to the Intel ® 82802AB/82802AC Firmware Hub (FWH) Datasheet or equivalent.

  • Page 205: Fwh Vpp Design Guidelines

    Due to the large routing solution space and necessity of a voltage translator in the design of a FWH on Intel® Pentium® M Processor / Intel® Celeron® M Processor and Intel 82801DBM ICH4-M based platforms, the following timing requirements must be met to ensure proper system operation.

  • Page 206: Rtc

    I/O Subsystem 9.8. The Intel 82801DBM ICH4-M contains a real time clock (RTC) with 256 bytes of battery backed SRAM. The internal RTC module provides two key functions: keeping date and time and storing system data in its RAM when the system is powered down.

  • Page 207: Rtc Crystal

    I/O Subsystem 9.8.1. RTC Crystal The Intel 82801DBM ICH4-M RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls. Figure 114 documents the external circuitry that comprises the oscillator of the ICH4-M RTC.

  • Page 208: External Capacitors

    The effect of changing the crystal’s frequency when operating at 0 C (25 C below room ° ° temperature) is the same when operating at 50 C (25 C above room temperature). ® Intel 855PM Chipset Platform Design Guide...

  • Page 209: Rtc Layout Considerations

    RTC circuit. Some recommendations are: 1. Reduce trace capacitance by minimizing the RTC trace length. The Intel 82801DBM ICH4-M requires a trace length less than 1 inch on each branch (from crystal’s terminal to RTCXn ball).

  • Page 210: Rtc External Rtcrst# Circuit

    RTCRST# CIRCUIT The Intel 82801DBM ICH4-M RTC requires some additional external circuitry. The RTCRST# signal is used to reset the RTC well. The external capacitor and the external resistor between RTCRST# and the RTC battery (VBAT) were selected to create an RC time delay, such that RTCRST# will go high some ®...

  • Page 211: Vbias Dc Voltage And Noise Measurements

    RTC. This will prevent these nodes from floating in G3, and correspondingly will prevent I RTC leakage that can cause excessive coin-cell drain. The PWROK input signal should also be configured with an external weak pull-down. ® Intel 855PM Chipset Platform Design Guide...

  • Page 212: Internal Lan Layout Guidelines

    9.9.1. Footprint Compatibility The Intel 82540EP Gigabit Ethernet Controller and the Intel 82551QM Fast Ethernet Controller are all manufactured in a footprint compatible 15 mm x 15 mm (1-mm pitch), 196-ball grid array package. Many of the critical signal pin locations on the 82540EP and the 82551QM are identical, allowing designers to create a single design that accommodates any one of these parts.

  • Page 213: Intel 82801Dbm Ich4-M - Lan Connect Interface Guidelines

    Special care must be given to matching the LAN_CLK traces to those of the other signals, as shown below. The following are guidelines for the Intel 82801DBM ICH4-M to LAN Connect Interface. The following signal lines are used on this interface:...

  • Page 214: Lom (Lan On Motherboard) Point-To-Point Interconnect

    I/O Subsystem 9.9.2.1.1. LOM (LAN On Motherboard) Point-To-Point Interconnect The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET are uniquely installed. Figure 118. Single Solution Interconnect LAN_CLK Platform Intel LAN_RSTSYNC ICH4-M Connect LAN_RXD[2:0] (PLC) LAN_TXD[2:0] Table 59.

  • Page 215: Crosstalk Consideration

    9.9.3. Intel 82562ET / Intel 82562 EM Guidelines For correct LAN performance, designers must follow the general guidelines outlined in Section 9.9.6. Additional guidelines for implementing an Intel 82562ET or Intel 82562EM Platform LAN Connect component are provided below. ®...

  • Page 216: Guidelines For Intel 82562Et / Intel 82562Em Component Placement

    For a noise free and stable operation, place the crystal and associated discrete components as close as possible to the Intel 82562ET/EM, keeping the trace length as short as possible and do not route any noisy signals in this area.

  • Page 217: Critical Dimensions

    There are two dimensions to consider during layout. Distance ‘A’ from the line RJ-45 connector to the magnetics module and distance ‘B’ from the Intel 82562ET or Intel 82562EM to the magnetics module. The combined total distances A and B must not exceed 4 inches (preferably, less than 2 inches). See Figure 121.

  • Page 218: Distance From Magnetics Module To Rj-45 (Distance

    If the Intel 82562ET must be placed further than a couple of inches from the RJ-45 connector, distance B can be sacrificed. Keeping the total distance between the Intel 82562ET and RJ-45 will as short as possible should be a priority.

  • Page 219: Terminating Unused Connections

    9.9.3.5.2. Termination Plane Capacitance Intel recommends that the termination plane capacitance equal a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused pairs of the RJ-45. Pads may be placed for an additional capacitance to chassis ground, which may be required if the termination plane capacitance is not large enough to pass EFT (Electrical Fast Transient) testing.

  • Page 220: Intel 82562Et/Em Disable Guidelines

    Rpack ± Ω There are four pins which are used to put the Intel 82562ET/EM controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational/disable features for this design. The four control signals shown in the below table should be configured as follows: Test_En should be pulled-down through a 100- resistor.

  • Page 221: Design And Layout Consideration For Intel 82540Ep / 82551Qm

    9.9.5. Design and Layout Consideration for Intel 82540EP / 82551QM For specific design and layout considerations for the Intel 82540EP Gigabit Ethernet Controller and the Intel 82551QM Faster Ethernet Controller, please refer to the following documents: 82551QM / 82540EM Interchangeable LOM Design Application Note (AP 432) (Reference...

  • Page 222: Trace Geometry And Length

    Isolate I/O signals from high speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals. Avoid routing high-speed LAN traces near other high-frequency signals associated with a video controller, cache controller, CPU, or other similar devices. ® Intel 855PM Chipset Platform Design Guide...

  • Page 223: Magnetics Module General Power And Ground Plane Considerations

    There should not be a power plane under the magnetics module. ® Intel 855PM Chipset Platform Design Guide...

  • Page 224: Common Physical Layout Issues

    10. Use of capacitor that is too large between the transmit traces and/or too much capacitance from the magnetic's transmit center-tap (on the Intel 82562ET side of the magnetics) to ground. Using capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall time so much that they fail the IEEE rise time and fall time specs.

  • Page 225: Power Management Interface

    If an Intel® Pentium® M Processor / Intel® Celeron® M Processor ITP700FLEX debug port is implemented on the system, Intel recommends that the DBR# signal of the ITP interface be connected to SYS_RESET# as well. If SYS_RESET# is implemented, a weak pull-up resistor pulled- up to the 3.3-V standby rail (VccSUS3_3) should also be implemented to ensure that no potential...

  • Page 226: Cpu I/O Signals Considerations

    9.11. CPU I/O Signals Considerations The Intel 82801DBM ICH4-M has been designed to be voltage compatible with the CMOS signals of the processor. For Intel Pentium M/Intel Celeron M processor-based systems, the ICH4-M’s V_CPU_IO rail uses the same 1.05-V voltage as the V rails for the processor and Intel 855PM chipset.

  • Page 227: Figure 127. Intel 82801Dbm Ich4-M Cpu Cmos Signals With Cpu And Fwh

    I/O Subsystem Figure 127. Intel 82801DBM ICH4-M CPU CMOS Signals with CPU and FWH V_CPU_IO @ 1.05V Intel Intel FERR# Pentium M ICH4-M Output Signals processor ® Intel 855PM Chipset Platform Design Guide...
  • Page 228 I/O Subsystem This page intentionally left blank. ® Intel 855PM Chipset Platform Design Guide...

  • Page 229: Platform Clock Routing Guidelines

    Platform Clock Routing Guidelines Platform Clock Routing Guidelines 10.1. Clock Routing Guidelines Only one clock generator component is required in an Intel 855PM chipset based system. Clock ® synthesizers that meet the Intel CK-408 Clock Synthesizer/Driver Specification are suitable for an Intel 855PM chipset based system.

  • Page 230: Table 62. Platform System Clock Cross-Reference

    AGP Connector or AGP Device PCIF ICH4-M PCICLK CLK33 PCI_CLK ICH4-M CLK14 CLK14 REF0 CLOCKI PCI Connector or PCI Device #1 PCICLK PCI Connector or PCI Device #2 PCI Connector or PCI Device #3 USBCLK ICH4-M CLK48 ® Intel 855PM Chipset Platform Design Guide...

  • Page 231: Figure 128. Platform Clock Topology Diagram

    66 MHz 66Buff ICH4-M 66 MHz 66Buff CLK66 33 MHz PCICLK PCIF 48 MHz CLK48 14.318 MHz CLK14 Connectors 33 MHz 33 MHz 33 MHz 14.318 MHz REFO CLOCKI 33 MHz PCI_CLK 33 MHz ® Intel 855PM Chipset Platform Design Guide...

  • Page 232: Clock Group Topology And Layout Routing Guidelines

    The clock synthesizer provides three pairs of 100-MHz differential clock outputs utilizing a 0.7-V voltage swing. The 100-MHz differential clocks are driven to the Intel Pentium M/Intel Celeron M processor, the Intel 855PM MCH, and the processor debug port with the topology shown in the figure below.

  • Page 233: Table 63. Bclk/Bclk#[1:0] Routing Guidelines

    MCH BCLK (L1 + L2 + L4) and BCLK# (L1’ + L2’ ± 10 mils + L4’) Length Matching Series Termination Resistor (Rs) ± 5% Figure 129 Parallel Termination Resistor (Rt) 49.9 ± 1% (for 55 MB impedance) Figure 129 NOTES: ® Intel 855PM Chipset Platform Design Guide...

  • Page 234: Bclk Length Matching Requirements

    If the BCLK traces vary within the tolerances specified, both traces of a differential pair must vary equally. 11. Values are based on socket dimensions/tolerances/parasitics outlined in the Intel® Mobile Processor Micro- FCPGA Socket (mPGA479M) Design Guidelines (Order number: 298520). Or in general terms, a 4mm ± 5% socket with lumped parasitics model.

  • Page 235: Bclk General Routing Guidelines

    EMI reduction: 1. Maintain uniform spacing between the two halves of differential clocks. 2. Route clocks on physical layer adjacent to the VSS reference plane only. Figure 130. Clock Skew as Measured from Agent-to-Agent ® Intel 855PM Chipset Platform Design Guide...

  • Page 236: Clk66 Clock Group

    The driver is the clock synthesizer 66-MHz clock output buffer and the receiver is the 66-MHz clock input buffer at the Intel 855PM MCH and the Intel 82801DBM ICH4-M. Note that the goal is to have as little skew between the clocks within this group as possible.

  • Page 237: Agpclk Clock Group

    CLK66. Figure 132. AGPCLK to AGP Connector Topology Trace on AGP Card Clock Driver Connector Device Figure 133. AGPCLK to AGP Device Down Topology Clock Driver Device ® Intel 855PM Chipset Platform Design Guide...

  • Page 238: Clk33 Clock Group

    Note: The goal is to have minimal (~ 0) skew between the clocks within this group, and also minimal (~ 0) skew between the clocks of this group and that of group CLK66. ® Intel 855PM Chipset Platform Design Guide...

  • Page 239: Pciclk Clock Group

    PCI devices on the PCI cards. Note that the goal is to have a maximum of ±1 ns skew between the clocks within this group, and also a maximum of ± 1 ns skew between the clocks of this group and that of group CLK33. ® Intel 855PM Chipset Platform Design Guide...

  • Page 240: Figure 135. Pciclk Group To Pci Device Down Topology

    Skew Requirements ± 1 ns of skew between the clocks of this group and those of CLK33 NOTE: Recommended resistor values and trace lengths may change in a later revision of the design guide. ® Intel 855PM Chipset Platform Design Guide...

  • Page 241: Figure 136. Pciclk Group To Pci Slot Topology

    Skew Requirements ± 1 ns of skew between the clocks of this group and those of CLK33 NOTE: Recommended resistor values and trace lengths may change in a later revision of the design guide. ® Intel 855PM Chipset Platform Design Guide...

  • Page 242: Usbclk Clock Group

    Figure 137 None – USBCLK is asynchronous to any Skew Requirements other clock on the platform NOTE: Recommended resistor values and trace lengths may change in a later revision of the design guide. ® Intel 855PM Chipset Platform Design Guide...

  • Page 243: Clk14 Clock Group

    NOTE: Recommended resistor values and trace lengths may change in a later revision of the design guide. 10.2.8. CK-408 Clock Chip Decoupling See Section 11.7.9 for details. ® Intel 855PM Chipset Platform Design Guide...

  • Page 244: Updates For Systems Based On Intel Pentium M Processor / Intel Celeron M Processor And Intel 855Pm Chipset

    10.4. CK-408 PWRDWN# Signal Connections For Intel Pentium M processor / Intel Celeron M processor based systems that support the S1M state, the PWRDWN# input of the CK-408 clock chip is required to be driven by both the SLP_S1# and SLP_S3# signals from the Intel 82801DBM ICH4-M, i.e.

  • Page 245: Platform Power Delivery Guidelines

    During Full-Power operation, all components remain powered. Full-power operation includes both Full- On and the S1M (CPU Stop-Grant state). Suspend operation: During suspend operation, power is removed from some components on the motherboard. Intel 855PM ® chipset-based systems can be designed to support a number of suspend states such as Power-On- Suspend (S1M), Suspend-to-RAM (S3), Suspend-to-Disk (S4), and Soft-Off (S5).

  • Page 246: Platform Power Requirements

    11.2. Platform Power Requirements The following figure shows the power delivery architecture for an example Intel 855PM chipset platform. This power delivery architecture supports the “Instantly Available PC Design Guidelines” via the S3 system state. To ensure that enough power is available during S3, a thorough power budget should be completed.

  • Page 247: Platform Power Delivery Architectural Block Diagram

    13-Bit Hub Interface 266MB/s ICH4-M +V3.3 +V1.05S +V3.3S +V1.5S +V1.5 +V1.5LAN ATA 66/100 +V1.8S PCI Bus +V3.3S Moon2 +V3.3 +V3.3S +V5S +V3.3LAN +V5S +V5S +VCC_RTC AC97 CardBus +V3.3 +V3.3Always +V3.3 +V3.3 +V3.3Always +V3.3S +V3.3Always ® Intel 855PM Chipset Platform Design Guide...

  • Page 248: Voltage Supply

    HIGH ON/OFF S4 (STD) HIGH ON/OFF S5 (Soft Off) ON/OFF 11.4. Intel 855PM MCH / 82801DBM ICH4-M Platform Power- Up Sequence Figure 140 describes the power-on timing sequence for an Intel 855PM/82801DBM-based platform. ® Intel 855PM Chipset Platform Design Guide...

  • Page 249: Figure 140. Intel 855Pm/82801Dbm Platform Power-Up Sequence

    T186 CPUSLP# T184 Frequency Strap Values Normal Operation Straps T185 PCIRST# T178 T181 SUS_STAT# T177 PWROK, VGATE T176 SLP_S3# T183b T181 T18 3a SLP_S4# SLP_S5# T183 Running SUSCLK T182 RSMRST#, RSM_PWROK T173 VccSus ® Intel 855PM Chipset Platform Design Guide...

  • Page 250: Table 72. Timing Sequence Parameters For Figure 140

    RTCRST# and the RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms. These transitions are clocked off the internal RTC. One RTC clock is approximately 32 µs. This transition is clocked off the 66-MHz CLK66. One CLK66 is approximately 15 ns. ® Intel 855PM Chipset Platform Design Guide...

  • Page 251: Intel 82801Dbm Ich4-M Power Sequencing Requirements

    ICH4-M. It is generally good design practice to power up the core before or at the same time as the other rails. 11.4.1.2. / 3.3 V Sequencing 5REF is the reference voltage for 5 V tolerance on inputs to the Intel 82801DBM ICH4-M. V must 5REF 5REF be powered up before V , or after V within 0.7 V.

  • Page 252: Figure 142. V5Ref_Sus With 5V_Always Connection Option

    USB D+ USB D+ USB D+ Intel recommended Intel recommended USB interface USB interface USB D- USB D- USB D- USB D- circuits circuits Note: D1 and D2 are BAT54 or Equivalent Schottky Diodes ® Intel 855PM Chipset Platform Design Guide...

  • Page 253: Intel 855Pm Mch Power Sequencing Requirements

    No Intel 855PM MCH power sequencing requirements exist for the system incorporating the Intel 855PM chipset. All MCH power rails should be stable before de-asserting reset, but the power rails can be brought up in any order desired. Good design practice would have all MCH power rails come up as close in time as practical, with the core voltage (1.2 V) coming up first.

  • Page 254: Ddr Power Delivery Design Guidelines

    11.5. DDR Power Delivery Design Guidelines The main focus of these Intel 855PM MCH guidelines is to minimize signal integrity problems and improve the power delivery to of the MCH system memory interface and the DDR SO-DIMMs. Some sections summarize the DDR system voltage and current requirements as of publishing for this document.

  • Page 255: Ddr Interface Decoupling Guidelines

    Intel 855PM MCH VCCSM Decoupling Guidelines Every Intel 855PM MCH ground and VCCSM power ball in the system memory interface should have its own via. For the VCCSM pins of the MCH, a minimum of fifteen 0603 form factor 0.1- F high frequency capacitors is required and must be placed within 150 mils of the MCH package.

  • Page 256: Ddr Reference Voltage

    Table 75 through Table 77 below have grouped the voltage and current specifications together for each the Intel 855PM MCH, memory, and termination voltages. There are seven voltages/power rails specified here for a DDR VR system. Although, there are only two unique voltage regulators for 2.5 V and 1.25 V nominal, each specific power rail described here has a unique specification.

  • Page 257: Table 75. Ddr Sdram Memory Supply Voltage And Current Specification

    MAX RELATIVE SPEC (calculated from (measured Vdd/2) + 0.050 measured "Vdd" value) MIN RELATIVE SPEC (calculated from (measured Vdd/2) - 0.050 measured "Vdd" value) (max) (max) (max) Absolute Maximum Current Requirements 0.920 0.001 (1mA) 5.000 ® Intel 855PM Chipset Platform Design Guide...

  • Page 258: Table 76. Mch System Memory Supply Voltage And Current Specification

    0.04 V Min Relative Spec (calculated from measured "VCCSM" (measured Vref) - value) (measured VCCSM/2) - 2% 0.040 V (max) (max) (max) VCCSM SMVREF TTRC Absolute Maximum Current Requirements 1.900 0.00005 (50uA) 0.080 (80mA) ® Intel 855PM Chipset Platform Design Guide...

  • Page 259: Smvref Design Recommendations

    11.5.3.1. SMVREF Design Recommendations There are two SMVREF pins on the Intel 855PM MCH that are used to set the reference voltage level for the DDR system memory signals (SMVREF). The reference voltage must be supplied to both SMVREF pins. The voltage level that needs to be supplied to these pins must be equal to VCCSM/2.

  • Page 260: Table 78. Intel 855Pm Mch System Memory I/O

    Leakage: This is the amount of leakage current which needs to sourced from the 2.5-V supply, across the divider’s top resistor (Rtop) and out to the Intel 855PM MCH SMVREF input or the DDR VREF input. This current does not go across the bottom resistor.

  • Page 261: Ddr Vref Requirements

    100-µA range. Today, it is not possible to guarantee this type of current requirement for these applications. Therefore, the use of a buffer is highly recommended for these reference voltage requirements. ® Intel 855PM Chipset Platform Design Guide...

  • Page 262: Ddr Smrcomp Resistive Compensation

    1.25-V source, VTT, at the end of the memory channel opposite the Intel 855PM MCH. It is recommended that VTT be generated from the same source as that used for VCCSM, and do not be shared with the MCH and DDR SMVREF. SMVREF has a much tighter tolerance and VTT can vary more easily depending on signal states.

  • Page 263: Vtt Rail Power Up Sequencing During Resume

    SCKE signals. These reference voltages and resistive compensation are necessary in order for the Intel 855PM MCH and the memory devices to recognize the valid assertion of SCKE to a logic ‘1’. SCKE must not glitch during resume and must rise monotonically.

  • Page 264: Figure 145. Decoupling Capacitors Placement And Connectivity

    PCI 6 T 48 VddA 48 MHz 66Buff0 / 3V66_2 48 MHz 66Buf 3V66_1 / f1 / 3V66_ 3 66Buf PCI_Sto f2 / 3V66_ 66In / 3V66 3V66_5 PWRD VddA SDAT Vtt_Pwr gd # ® Intel 855PM Chipset Platform Design Guide...

  • Page 265: Decoupling Recommendations

    This condition could cause the component voltage rails to drop below specified limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins. Intel recommends that the developer use the amount of decoupling capacitors specified in Table 83 to ensure the component maintains stable supply voltages.

  • Page 266: Figure 146. Minimized Loop Inductance Example

    Layer 1 4.5 mils nominal Layer 2 48 mils nominal Layer 3 Layer 4 Current Flow to Decoupling Cap Table 83. Decoupling Requirements for the Intel 82801DBM ICH4-M Decoupling Decoupling Type (Pin type) Decoupling Placement Requirements VCC3_3 (6) 0.1 µF...

  • Page 267: Ddr Vtt High Frequency And Bulk Decoupling

    All VCC pins should be connected to the same power supply. All VSS pins should be connected to the same ground plane. Four to six decoupling capacitors, including two 4.7-µF capacitors are recommended Place decoupling as close as possible to power pins. ® Intel 855PM Chipset Platform Design Guide...

  • Page 268: Ck-408 Clock Driver Decoupling

    One 10-µF bulk decoupling cap in a 1206 package placed close to the VDDA generation circuitry 11.8. Intel 855PM MCH Power Consumption Numbers The following table shows the Intel 855PM MCH power consumption estimates. Table 84. Intel 855PM MCH Power Consumption Estimates Power Plane...

  • Page 269: Intel 82801Dbm Ich4-M Power Consumption Numbers

    Platform Power Delivery Guidelines 11.9. Intel 82801DBM ICH4-M Power Consumption Numbers The following table shows the Intel 82801DBM ICH4-M power consumption estimates. Table 85. Intel 82801DBM ICH4-M Power Consumption Estimates Power Plane Maximum Power Consumption S4/S5 Vcc1_5 Core 550 mA...

  • Page 270: Thermal Design Power

    It does not represent the expected power generated by a power virus. The thermal design power number for the Intel 855PM MCH and Intel 82801DBM ICH4-M are listed below. Table 86. Intel 855PM MCH Component Thermal Design Power...

  • Page 271: Intel Pro/Wireless 2100 And Bluetooth Design Requirements

    12.1. PCB Interface Requirements Two PCB traces shall be used to carry channel number and clock signals between Bluetooth and Intel PRO/Wireless 2100. Although these traces do not need to match any length, width or impedance constraints a typical width of 5 mils and spacing of 5 mils is recommended. Pin # 43 of the mPCI connector needs to be routed to the Channel_Data signal of the Bluetooth module.

  • Page 272: Selective Suspend Support

    RF Disable Support Requirements for Intel PRO/Wireless 2100 and Bluetooth Devices The RF Disable interface to the Intel PRO/Wireless 2100 module occurs via pin 13 of the mini-PCI connector. This interface provides support to disable the Intel PRO/Wireless 2100 radio through methods including, but not limited to, an external mechanical switch or button on the notebook or through an embedded controller.

  • Page 273: Reserved, Nc, And Test Signals

    Intel Pentium M Processor and Intel Celeron M RSVD Signals The Intel Pentium M processor / Intel Celeron M processor has a total of three TEST and seven RSVD signals that are Intel reserved in the pin-map. All other RSVD signals are to be left unconnected but should have access to open routing channels for possible future use.

  • Page 274: Intel 855Pm Mch Rsvd Signals

    Intel 855PM MCH RSVD Signals The Intel 855PM MCH has a total of nine RSVD and two NC signals that are Intel reserved in the pin- map. The recommendation is to provide test points for all RSVD signals for possible future use. All NC signals should be left as no connects.

  • Page 275: Platform Design Checklist

    The following checklist provides design recommendations and guidance for the Intel Pentium M processor / Intel Celeron M processor systems with the Intel 855PM chipset platform. It should be used to ensure that design recommendations in this design guide have been followed prior to schematic reviews.

  • Page 276: Customer Implementation

    14.3. Design Checklist Implementation The voltage rail designations in this design checklist were intended to be as general as possible. The following table describes the equivalent voltage rails in the Intel CRB schematics attached in this design guide. Checklist Rail...

  • Page 277: Intel Pentium M Processor And Intel Celeron M Processor

    Platform Design Checklist 14.4. Intel Pentium M Processor and Intel Celeron M Processor 14.4.1. Resistor Recommendations Intel Pentium M/Intel Celeron M Processor – Resistor Recommendations Pin Name System Series Termination Notes Resistor ( Pull up/Pull down A20M#, Point-to-point connection to ICH4-M.
  • Page 278 Platform Design Checklist Intel Pentium M/Intel Celeron M Processor – Resistor Recommendations Pin Name System Series Termination Notes Resistor ( Pull up/Pull down be placed between the receiver and termination resistor. Series resistor should have no stub when connecting to the FERR# trace from the CPU.
  • Page 279 Platform Design Checklist Intel Pentium M/Intel Celeron M Processor – Resistor Recommendations Pin Name System Series Termination Notes Resistor ( Pull up/Pull down Point-to-point connection to system receiver. If Voltage Translation Is Required: Driver isolation resistor should be placed at the beginning of the T-split to the system receiver.
  • Page 280 Platform Design Checklist Intel Pentium M/Intel Celeron M Processor – Resistor Recommendations Pin Name System Series Termination Notes Resistor ( Pull up/Pull down If ITP Not Supported: See Section 14.4.2.3. If ITP700FLEX Is Used: See Section 14.4.2.1. If ITP Interposer Is Used: See Section 14.4.2.2.
  • Page 281 Platform Design Checklist Intel Pentium M/Intel Celeron M Processor – Resistor Recommendations Pin Name System Series Termination Notes Resistor ( Pull up/Pull down VCC[71:0] Tie to 72 VCC pins VCC[Vcc_Core] VCCA[3:0] Tie to Vcc1_8 See layout example in Section 5.3.

  • Page 282: Figure 148. Processor Gtlref Voltage Divider Network

    RSVD (pin AD26) (pin AC1) Intel Pentium M processor RSVD RSVD (pin E26) (pin G1) Figure 149. Routing Illustration for INIT# Intel 3.3V V_IO_FWH 3.3V Intel Intel Pentium M ICH4-M processor 3904 3904 ® Intel 855PM Chipset Platform Design Guide...

  • Page 283: Figure 65. Processor

    +/- 5% 1.3K ohm To Receiver +/- 5% 330 ohm 3904 +/- 5% From Driver 3904 Figure 151. Routing Illustration for PROCHOT# System Receiver 3.3V V_IO_RCVR Intel 3.3V Pentium M Processor VCCP 3904 3904 ® Intel 855PM Chipset Platform Design Guide...

  • Page 284: In Target Probe (Itp)

    Pull down to GND 27.4 ± 1% ITP700FLEX supported Validation Systems: (IF ITP700FLEX Parallel termination resistor placed IS USED) within ±200 ps of ITP700FLEX. ITP700FLEX supported Production (IF ITP700FLEX Systems: IS NOT USED) ® Intel 855PM Chipset Platform Design Guide...
  • Page 285 Parallel termination resistor placed within 2.0” of CPU pin. See Section 4.3.1.1 and 4.3.1.4 for details. TRST# Pull down to GND - 680 ITP700FLEX supported Validation Systems: (IF ITP700FLEX Parallel termination resistor can be IS USED) ® Intel 855PM Chipset Platform Design Guide...
  • Page 286 See section 4.3.1.1 for more details. NOTES: See Section 14.4.2.2 if ITP Interposer is implemented. See Section 14.4.2.3 if NO processor ITP debug port solution is implemented. Default tolerance for resistors is +/-5% unless otherwise specified. ® Intel 855PM Chipset Platform Design Guide...

  • Page 287: Itp Interposer

    NOTES: 1. See Section 14.4.2.1 if ITP700FLEX connector is implemented. 2. See Section 14.4.2.3 if NO processor ITP debug port solution is implemented. 3. Default tolerance for resistors is +/-5% unless otherwise specified. ® Intel 855PM Chipset Platform Design Guide...

  • Page 288: Required Strapping When Itp Debug Port Disable

    0603 MLCC, >= X7R. Place all capacitors next to CPU. Also see Section 14.6.4 for VCCP decoupling requirement at the MCH. See Section 5.9.4 for details on Intel processor and MCH VCCP voltage plane ® Intel 855PM Chipset Platform Design Guide...
  • Page 289 Platform Design Checklist Decoupling Recommendations Signal Configuration Notes and decoupling. ® Intel 855PM Chipset Platform Design Guide...

  • Page 290: Clock Checklist

    PWRDWN# If S1M Is Supported: This signal should be driven by the logical AND of the ICH4-M’s SLP_S1# and SLP_S3# signals. See Figure 152. If S1M Is NOT Supported but S3 is supported: ® Intel 855PM Chipset Platform Design Guide...
  • Page 291 Also see Section 14.5.2 for decoupling See Notes requirement. CK-408 Clock – GND Signals VSS[5:0] Tie to GND VSSA Tie to GND VSSIREF Tie to GND NOTE: Default tolerance for resistors is +/-5% unless otherwise specified. ® Intel 855PM Chipset Platform Design Guide...

  • Page 292: Decoupling Recommendation

    Figure 152. Clock Power Down Implementation Vcc3_3Sus / V3ALWAYS PM_SLP_S1# CLK_PWRDWN# PM_SLP_S3# 14.5.2. CK-408 Decoupling Recommendation Platform recommendations and decoupling guidelines provided by your CK-408 vendor should be adhered to ensure proper operation of your clock chip. ® Intel 855PM Chipset Platform Design Guide...

  • Page 293: Intel 855Pm Mch Checklist

    Platform Design Checklist 14.6. Intel 855PM MCH Checklist 14.6.1. System Memory 14.6.1.1. MCH System Memory Interface Intel 855PM MCH – System Memory Interface Pin Name System Series Notes Resistor ( Pull up/Pull down RCVENIN# Point to point connection to RCVENOUT#.
  • Page 294 Pull up to Two routing topologies available for these Vcc1_25[DDR_Vtt] signals. See Section 6.1.3 for routing requirements. Intel 855PM MCH – System Memory Clock Signals SCK[5:0], These differential clock signals can be routed to SCK[5:0]# any SO-DIMM provided that the BIOS understands the routing implementation.

  • Page 295: Figure 153. Reference Voltage Level For Smvref[1:0]

    Platform Design Checklist Figure 153. Reference Voltage Level for SMVREF[1:0] Vcc2_5/VccSus2_5 Intel 10k+/-1% 855PM SMVREF SMVREF0 10k+/-1% SMVREF1 ® Intel 855PM Chipset Platform Design Guide...

  • Page 296: Ddr So-Dimm Interface

    These signals can be left as NC (No Connect). DDR SO-DIMM – Reference Voltage Signals VREF[2:1] See Notes In S3, VREF[2:1] are powered ON in Intel CRB. Reference voltage = (VccSus2_5 ± 8%) / 2 ± 4%. Note that a buffer is used to provide the necessary current and reference voltage to VREF.
  • Page 297 SPD EEPROM Address Detection: Connect to VCC3_3 See Notes For 1st SO-DIMM address ‘A0’: SA[2:0] should be tied to GND For 2nd SO-DIMM address ‘A2’: SA[0] – Tie to VCC3_3 SA[2:1] – Tie to GND ® Intel 855PM Chipset Platform Design Guide...

  • Page 298: Miscellaneous Signals

    TESTIN This signal can be left as NC (No Connect). Power Signals VCC[9:0] Tie to See Section 14.6.4 for VCC_MCH decoupling Vcc1_2[Vcc_mch] requirements. VTT[19:0] Tie to VCCP Ground Signals VSS[141:0] Tie to GND ® Intel 855PM Chipset Platform Design Guide...

  • Page 299: Figure 154. Intel 855Pm Mch Hswng[1:0] Reference Voltage Generation Circuit

    Platform Design Checklist Figure 154. Intel 855PM MCH HSWNG[1:0] Reference Voltage Generation Circuit +VCCP +VCCP 301Ω 0.1uF 0.1 uF HSWNG[0] HSWNG[1] Intel HSWNG[0] HSWNG[1] 855PM 150Ω Figure 155. Intel 855PM MCH HVREF[4:0] Generation Circuit +VCCP Ω MCH_GTLREF AB16 HVREF Intel...

  • Page 300: Resistive Compensation

    See Section 4.1.8.2 for details. SMRCOMP Pull up to 30.1 ± 1% In S3, Vcc1_25[DDR_Vtt] (DDR channel termination Vcc1_25[DDR_Vtt] voltage) can be turned OFF. One 0.1 µF decoupling cap is required for this signal. ® Intel 855PM Chipset Platform Design Guide...

  • Page 301: Decoupling Recommendations (Mch)

    Place one 0.1 µF close to every 2 pull up resistors terminated to Vcc1_25[DDR_Vtt]. See Section 11.7.4 for details. VccSus2_5 0.1 µF Place capacitors between the SO-DIMMs . See Section 11.5.1.2 for details. ® Intel 855PM Chipset Platform Design Guide...

  • Page 302: Mch Reference Voltage

    See Figure 155. ± 1% (bottom) R1a = 49.9 ± 1% R2a = 100 ± 1% C1 = 200 pF C2 = 200 pF C3 = 1 µF See Section 4.1.7 for routing requirements. ® Intel 855PM Chipset Platform Design Guide...

  • Page 303: Agp Interface

    SB_STB# See Notes Connect directly to AGP controller. MCH has an internal pull down. External pull down is NOT required. Intel(R) Intel 855PM MCH AGP Interface – Power Signals VCCAGP[15:0] Tie to Vcc1_5 Also see Section 11.7.5 for decoupling requirement.

  • Page 304: Agp Connector

    AGP controllers that implement these signals. INTA#, INTB# Route to the ICH4-M PIRQ signals. 14.7.1.2. AGP Decoupling Recommendations Intel 855PM MCH Interface – High Frequency Decoupling Recommendations Pin Name Configuration Notes Vcc1_5 Pull down to GND 0.01 µF...

  • Page 305: Figure 156. Agpref Implementation (On Intel Crb)

    Platform Design Checklist Figure 156. AGPREF Implementation (On Intel CRB) Vcc1_5 1KΩ Intel 855PM AGPREF Vrefcg 1KΩ 0.1uF 0.1uF Place near MCH Place near AGP ® Intel 855PM Chipset Platform Design Guide...

  • Page 306: Ich4-M Checklist

    If XOR Chain Testing Is NOT Used: Pull down the signals through a shared 10-k resistor. If XOR Chain Testing Is Used: Each signal requires a separate 10-k pull down resistor. IRQ[15:14] Pull up to Vcc3_3 8.2 k - 10 k ® Intel 855PM Chipset Platform Design Guide...
  • Page 307 PIRQF#/GPIO3 External pull-up is required when muxed signal PIRQG#/GPIO4 (INT_PIRQ[E:H]#/ GPIO[2:5]) is implemented PIRQH#/GPIO5 as PIRQ. SERIRQ Pull up to Vcc3_3 8.2 k NOTE: Default tolerance for resistors is +/-5% unless otherwise specified. ® Intel 855PM Chipset Platform Design Guide...

  • Page 308: Gpio

    GPIO[28, 27, 25] From resume power well (V Sus3_3). (Note: use pull up to V 3_3 if this signal is pulled up) These signals are NOT 5-V tolerant. GPIO[25] can be used as AUDIO_PWRDN ® Intel 855PM Chipset Platform Design Guide...

  • Page 309: Agp Busy/Stop Design Requirements

    It can also be used as an indication that the peripherals should isolate their outputs that may be going to powered-off planes. NOTE: Please also consult Intel for the latest AGP Busy and Stop signal implementation. ® Intel...

  • Page 310: System Management Bus (Smbus) Interface

    Resistor change for faster rise time and to ensure timings are within specification. Value of pull up resistor is also determined by line load. Intel CRB uses 4.7 k pull up resistor. Please see Intel schematics page 18. The SMLink and SMBus signals must be tied together externally in S0 for SMBus 2.0 compliance:...

  • Page 311: Ac '97 Interface

    A series termination resistor is required for the PRIMARY CODEC. One series termination resistor (R2=R1) is required for the SECONDARY/ TERTIARY CODEC connector card if the resistor is not found on the connector card. See Section 9.3 for routing requirements. ® Intel 855PM Chipset Platform Design Guide...

  • Page 312: Ich4-M Power Management Interface

    10 ms after both Vcc3_3 and Vcc1_8 have reached their nominal voltages. Intel CRB uses a 100 k pull down to reduce leakage from coin cell battery in G3. Pull up to...
  • Page 313 If SYS_RESET# Is Used: A weak pull up is required to prevent the signal from floating. If SYS_RESET# Is NOT Used: Pull up to VccSus3_3 through a 100 k ® Intel 855PM Chipset Platform Design Guide...

  • Page 314: Fwh/Lpc Interface

    Tie signals together and pull down through a USBRBIAS# common 22.6 ± 1% resistor. The RBIAS resistor should be placed within 500 mils of the ICH4-M and avoid routing next to clock pins. ® Intel 855PM Chipset Platform Design Guide...

  • Page 315: Hub Interface

    3” away. Please see Figure 158. See page 8 and 15 in the Intel CRB schematics. HI_VSWING See Notes HIVREF, HI_VSWING and HI_REF(MCH signal) can share a common hub interface reference divider.

  • Page 316: Figure 66. Intel 855Pm Mch

    R1=R2=100 to 150         C1=0.01 uF C2=0.1 uF Figure 158. Hub Interface with Locally Generated Reference Voltage Divider Circuit HI=1.8V HI_VSWING HIREF Intel ICH4-M NOTES :: R1=R2=100 to 150  C1=0.01 uF C2=0.1uF ® Intel 855PM Chipset Platform Design Guide...

  • Page 317: 14.8.10. Rtc Circuitry

    Please note that peak-to-peak swing on RTCX1 cannot exceed 1.0 V CLK_VBIAS See notes Connect to CLK_RTCX1 through a 10-m resistor. Connect to Vbatt through a 1k ohms in series with a 0.047-µF capacitor. ® Intel 855PM Chipset Platform Design Guide...

  • Page 318: Figure 159 External Circuitry For The Rtc

    VCCRTC powers the RTC well of the ICH4-M 3.3V Sus is Active Whenever System Plugged In RTCX1 is the Input to the Internal Oscillator Vbatt is Voltage Provided By Battery RTCX2 is the feedback for the external crystal ® Intel 855PM Chipset Platform Design Guide...

  • Page 319: 14.8.11. Lan Interface

    Connect VCCLAN1.5[1:0] to the customer designated 1.5VLAN power rail Connect VCCLAN3.3[1:0] to the customer designated 3.3VLAN power rail If ICH4-M LAN connect interface is not used: Connect VCCLAN1.5[1:0] to Vcc1_5 Connect VCCLAN3.3[1:0] to Vcc3_3 ® Intel 855PM Chipset Platform Design Guide...

  • Page 320: 14.8.12. Primary Ide Interface

    Mobile IDE Swap See Section 9.1.4 for implementating the ICH4- Bay Support M’s IDE interface tri-state feature. This feature can be used for systems designed to support an IDE “hot” swap drive bay. ® Intel 855PM Chipset Platform Design Guide...

  • Page 321: Ide Interface (Secondary Ide Connector)

    Mobile IDE Swap See Section 9.1.4 contains recommendations Bay Support for implementating the ICH4-M’s IDE interface tri-state feature. This feature can be used for systems designed to support an IDE “hot” swap drive bay. ® Intel 855PM Chipset Platform Design Guide...

  • Page 322: 14.8.14. Miscellaneous Signals

    (0.5 * Vcc3_3 to Vcc3_3 + 0.5) ® Intel 855PM Chipset Platform Design Guide...

  • Page 323: 14.8.15. Ich4-M Power Signals & Decoupling Recommendations

    All decoupling guidelines are recommendations based on our reference board design. Customers will need to take their layout, and PCB board design into consideration when deciding on their overall decoupling solution Capacitors should be place less than 100 mils from the package ® Intel 855PM Chipset Platform Design Guide...

  • Page 324: Usb Checklist

    Each signal requires a LC Pi filter that consists of one 0.1 µF, one 100 µF and one ferrite bead in Intel CRB. See Figure 160 Both caps on Pin 2 of ferrite bead. Optimal decoupling achieve with 100 µF cap on connector side of ferrite bead.

  • Page 325: Decoupling Recommendations

    Damping Pull up/Pull down FGPI[4:0] See Notes Can be connected directly to GND In Intel CRB, each signal requires a 100 ohms pull down resistor. See Notes In Intel CRB, the signal requires a 10 kohms pull down resistor. RST# In Intel CRB, the signal requires a 100 ohms series damping resistor.

  • Page 326: Lan / Homepna Checklist

    Pin Name Configuration Notes VCC[2:1] Pull down to GND 0.1 µF In Intel CRB, two 0.1 µF s and one 4.7 µF VCCA capacitors are used for decoupling. The 4.7 µF decoupling recommendation is shared among all 5 signals. Please see Intel CRB schematics.

  • Page 327: 14.11.1.2. Decoupling Recommendations

    Platform Design Checklist Figure 161. LAN_RST# Design Recommendation (On Intel CRB) VccS us3_3LAN 82562E M IS O L_TC K IS O L_TI IS O L_E X LA N_R S T 14.11.1.2. Decoupling Recommendations LAN – Decoupling Recommendations Signal Name Configuration...
  • Page 328 Platform Design Checklist This page intentionally left blank. ® Intel 855PM Chipset Platform Design Guide...

  • Page 329: Intel Customer Reference Board Schematics

    Intel Customer Reference Board Schematics Intel Customer Reference Board Schematics See the following page for customer reference board schematics. ® Intel 855PM Chipset Platform Design Guide...

  • Page 330: Figure 67. Intel 855Pm Mch

    PG 14 PCPU PG 3,4 Header Thermal PG 35 Sensor PG 10 PG 10 PG 5 1.5V AGP 1.5V, 66MHz Intel 855PM SDRAM SLOT PG 9 593 uFCBGA PG 6,7,8 DDR VR Hub Interface PG 40 66MHz PG 23,24 ATA 100...
  • Page 331 +VCCP 1.05V rail for Processor I/O Thermal Diode 1001 110x SMB_THRM Smart Battery 0001 011x SMB_SB +V1.2S_MCH 1.2V For 855PM Core(off in S3-S5) Smart Battery Charger 0001 001x SMB_SB +V1.25 DDR Termination voltage(off in S4-S5) Smart Selector 0001 010x SMB_SB +V1.5S...
  • Page 332 Comp1 Pentium M-Processor Comp2 R387 R130 Comp3 NO_STUFF_1K NO_STUFF_1K +VCCP 4,5,7,15,16,17,37,39,42 R378 R377 R381 R379 54.9_1% 27.4_1% 54.9_1% 27.4_1% R532 Title NO_STUFF_150 Processor 1 of 2 Size Project: Document Number H_DPSLP# Custom 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 333 C173 C191 C161 C174 C159 C190 C192 VSS95 VSS96 0.01UF 0.01UF 0.01UF 0.01UF 10UF 10UF 10UF 10UF Pentium M-Processor 6,7,9,17,41 +V1.5S R397 NO_STUFF_0 Title Processor 2 of 2 Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 334 Note: Note: R169 should be place within 2.0" of the R171,C455,R172,R158,R170 processor; all others Title not needed for Customer Processor Thermal Sensor & ITP place near ITP Platforms Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 335 0.5" from 855PM AGP_SBSTB MCH_RSVD1 42 AGP_SBSTB# PCI_RST# 15,23,28,34,42 HUB_VREF_MCH 8 AGP_RBF# HUB_PSTRB# 8,15 AGP_WBF# HUB_PSTRB 8,15 AGP_PIPE# HUB_PD[10:0] 8,15 AGP_ST0 AGP_ST1 AGP_ST2 Title 855PM MCH (1 of 3) Size Project: Document Number Custom 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 336 R390 VCCHA VCCSM33 100_1% VCCSM34 C420 J3002 NO_STUFF_CON3_HDR 220PF 220PF VCCSM35 0.1UF C424 NO_STUFF_CON3_HDR VCCSM36 10UF R3004 VCCSM37 100_1% Title 9,15,17,20,24,27,29,32,34,36,40,41 +V3.3 855PM MCH (2 of 3) NO_STUFF_CON3_HDR Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 337 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF C451 PLACE C428 VSS66 VSS137 0.01UF NEAR MCH VSS67 VSS138 VSS68 VSS139 VSS69 VSS140 VSS70 VSS141 Title 855PM MCH (3 of 3) Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 338 100uF 0.1UF 0.1UF 0.1UF AGP_ST1 GND10 AGP_ST2 GND11 AGP CONN GND12 AGP_PIPE# PIPE# GND13 GND14 15,19,20,34 PCI_PME# PME# GND15 Title GND16 AGP 1.5V Connector USB- GND17 USB+ GND18 Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 339 SO DIMM 1 +V3.3S_SPD RSVD4 VDDID RSVD6 VDDSPD RSVD7 VREF1 R509 0 SM_VREF_DIMM_D SM_VREF_DIMM VREF2 GND0 C526 GND1 0.1UF RSVD4 RSVD4 RSVD5 RSVD5 RSVD6 RSVD6 Title RSVD7 DDR SO-DIMM RSVD7 Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 340 M_BS0# M_BS0_FR# 10 R463 6,10,12 M_BS1# M_BS1_FR# 10 R443 6,10,12 M_CAS# M_CAS_FR# 10 R444 6,10,12 M_RAS# M_RAS_FR# 10 R471 6,10,12 M_WE# M_WE_FR# 10 Title DDR SERIES TERMINATION Size Project: Document Number Custom 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 341 6,10 M_CKE2_R top side as close to RPACK as possible. 6,10,11 M_BS0# 6,10,11 M_BS1# 6,10,11 M_WE# 6,10,11 M_RAS# 6,10,11 M_CAS# Title DDR Parallel Termination Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 342 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C558 C563 C569 C583 C561 C593 C557 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Title DDR Decoupling Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 343 C238 NO_STUFF_10pF R181 CLK_ICH14 16 5,9,10,15,17,18,20,23,28,30,31,32,33,36,37,38,41,42 +V3.3S C243 NO_STUFF_10pF 16,24,41 PM_SLP_S1# CLK_PWRDWN# MULT Title IREF CK408 CLOCK SWING CONFIG CK-408 16,22,29,34,40,41 PM_SLP_S3# (R419) 74AHC1G08 Size Project: Document Number 0.7 VOLTS 475 1% 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 344 LAN_RST 27 LAN_RSTSYNC LAN_RST# PM_LANPWROK 27,29 ICH4-M ICH_PME# R297 INT_APICCLK 9,19,20,34 PCI_PME# INT_APICD0 INT_APICD1 6,23,28,34,42 PCI_RST# +V3.3 7,9,17,20,24,27,29,32,34,36,40,41 R483 R498 R494 Title 9,19,20,21,29,30,31,34 BUF_PCI_RST# ICH4-M (1 of 3) BUFFER Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 345 AC_SPKR 24 R340 GPIO43 PM_THRMTRIP#_D C597 depends ICH_GPIO43 GPIO43 THRMTRIP# on Crystal ICH4-M RTC_RST# C597 10PF RTC_VBIAS RTC_X1 RTC_X2 R313 32.768KHZ Title ICH4-M (2 of 3) C310 Size Project: Document Number 10PF 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 346 5,9,16,18,19,20,24,25,26,29,33,34,36,41 +V3.3ALWAYS R316 C302 C314 20k_1% 10UF U42D ICH4-M R320 R324 BSS138 POK_DQ V1.5_PWRGD BSS138 R318 POK_D CR13A CR13B 3904 3904 DC_SLP_S5# 40,41 Title ICH4-M (3 of 3) Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 347 4.7K 2.0 compliance. GND_V5A SMLINK1 15,19,20 FAB ID Strapping Table ICH_FAB_REV 9,14,20,24,34,41 +V12S BOARD FAB SMB_DATA 10,14,15,21 BSS138 +V3.3S_ICH 16,17,19,21,34 Title +V5_ALWAYS VR, ICH4-M Pullups and Testpoints Size Project: Document Number 855PM Platform CON4_HDR Date: Monday, February 24, 2003 Sheet...
  • Page 348 R425 R362 8.2K NO_STUFF_0 15,16 PCI_GNTA# PCI_REQA# 15 LEGACY HEADER INT_SERIRQ 15,20,21,29,31,34 FOR ADD-IN 5Pin_Keyed-HDR AUDIO CARD R424 TESTING 8.2K Title PCI Slot 1 & 2 16,17,18,21,34 +V3.3S_ICH Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 349 C172 C146 C160 C154 C148 C100 C101 C149 C185 C184 C186 22UF 22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 0.1UF Size Project: Document Number 0.1UF 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 350 PCI_REQ4# CLK_DOCKPCI DOCK_GNT4# 22 29,33,34 DOCK_INTR# DOCK_REQ4# 22 CLK_DOCKCONNPCI 22 DOCK_DOCKINTR# 22 2A10 2B10 1OE# 1OE# GND1 2OE# DOCK_QPCIEN# 2OE# GND2 Bus-Switch-74CBT3384 GND3 GND4 74CBTD16210 Title Docking Q-Switches Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 351 INTA# GND29 LPT_SLCT GND_USB GND21 V_ACDC2 LPT_STB# SUSTAT# UNDKRQ# V_ACDC3 CD4#/GND CD1# 200Pin_Docking-Plug 200Pin_Docking-Plug CR14 DOCK_SUSTAT# 14,16,29,34,40,41 PM_SLP_S3# There is pull-up on BAR43 docking station. Title Docking Connector Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 352 IDE_SDD0 IDE_SDD15 4.7K R3006 IDE_SDDREQ IDE_SDIOW# R304 IDE_SDIOR# IDE_SD_CSEL IDE_SIORDY IDE_SDDACK# 15,18,34 INT_IRQ15 IDE_SDA1 IDE_SATADET 16,34 IDE_SDA0 R302 IDE_SDCS1# IDE_SDACTIVE# 20x2-HDR IDE_SDCS3# IDE_SDA2 Title IDE 1 of 2 Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 353 0.1 to 0.4 inches from MDC AC_SHUT bit is set header based on topology to 1 AC_BITCLK +V5S_IDE_S R303 Title IDE_SDACTIVE#_Q IDE 2 of 2 / MDC INTERPOSER IDE_SDACTIVE# Size Project: Document Number GREEN 855PM Platform Monday, February 24, 2003 Date: Sheet...
  • Page 354 Clamping-Diode Clamping-Diode 17,18,26 +V5_ALWAYS RP6A RP6B USB_OC0# 16 FB16 50OHM OC1# USBPWR_CONNC USBC_VCC OUT1 EN1_B Title OUT2 USB (1 of 2) EN2_B OC2# C337 OC2# Size Project: Document Number TPS2052 0.1UF 100uF 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 355 CR33 BOTTOM C335 PORT GND11 0.1UF 100uF STACKED_RJ45_USB Clamping-Diode Clamping-Diode USBB- USB_PN4 USBB+ USB_PP4 90@100MHz CR34 CR35 Clamping-Diode 5,9,16,17,18,19,20,24,25,29,33,34,36,41 +V3.3ALWAYS Clamping-Diode R455 USB_OC5# Title USB (2 of 2) Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 356 LED resistors BSS138 15,29 PM_LANPWROK R344 Chassis GND are integrated (should cover part 82562EM into RJ-45 of magnetics) 25MHZ 22PF 22PF NO_STUFF 82562EM Testpoint Header Title LAN Interface (82562EM) Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 357 TP_FWH_NC2 RSVD5 TP_FWH_RSVD4 TP_FWH_NC3 RSVD4 TP_FWH_RSVD3 TP_FWH_NC4 RSVD3 TP_FWH_NC5 TP_FWH_NC6 R479 GND2 TP_FWH_NC7 GND1 TP_FWH_NC8 GNDA FWH SKT FWH sits in the Title FWH_TSOP_Socket, Size Project: Document Number Not on the board 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 358 GATE OFF PCIRST# during S3 Title SMC_PROG_RST# TP_KSC_RES0 System Management and Keyboard Controller TP_KSC_P76 SMC_MD TP_NMI_GATE# Note: for flash progamming, must use Size Project: Document Number 855PM Platform TX1 and RX1, which are pin97 and pin98. CON14_RECEPT NO_STUFF_CON3_HDR Date: Monday, February 24, 2003 Sheet...
  • Page 359 LPC_AD3 16,28,29,31,34 RIGHT GND1 LPC_AD2 16,28,29,31,34 GND2 LPC_AD1 16,28,29,31,34 C438 C426 C450 GND3 LPC_AD0 16,28,29,31,34 0.1UF 0.1UF 0.1UF GND4 Title SMC Suspend Timer and Port 80 LEDs EPM7032AE Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 360 SIO_LED_VID4 42 SIO_LED_VID3 42 SIO_LED_VID2 42 +V3.3S 5,9,10,14,15,17,18,20,23,28,30,32,33,36,37,38,41,42 SIO_LED_VID1 42 SIO_LED_VID0 42 +V3.3S_SIO SIO_LED_VID5 42 IDE_SPWR_EN# 24,34 R220 0.01_1% C471 C467 C221 Title 0.1UF 0.1UF 22UF Super I/O Controller Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 361 R2OUTB is enabled even in suspend. Title SER_RIA# is routed to allow the system to Floppy, Parallel, Serial, and IR Ports wake up in Suspend To RAM. Size Project: Document Number 855PM Platform Note: FORCEOFF# overrides FORCEON. Date: Monday, February 24, 2003 Sheet...
  • Page 362 PS/2 mouse. Otherwise, the keyboard PS/2 4.7K 4.7K connector will only support a PS/2 keyboard. FB14 FB11 60ohm@100MHz 60ohm@100MHz MOUSE_CLK MOUSE_DATA CP1D CP1B 47PF 47PF Title Keyboard and Mouse Connectors Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 363 SMC Sidebands for LPC Power Management 17,18,19,20,24,40,41 +V5_LPCSLOT +V3.3 7,9,15,17,20,24,27,29,32,36,40,41 +V3.3_LPCSLOT R210 0.01_1% R233 0.01_1% Title C270 C261 C287 C218 C220 C276 LPC Slot & Debug Headers 22UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 364 Fan Power Control 9,17,20,21,24,31,32,33,36,37,38,41,42 +V5S +V5_FAN C200 C199 R125 C205 0.1UF 22UF 1000PF SI3457DV CR15 1N4148 R127 FAN_ON_D 100K CONN2_HDR BSS138 29,34 FAN_ON Title Fan Circuit Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 365 1.324 0.812 1.308 0.796 R3007 R3008 1.292 0.780 1.276 0.764 Title 20x2_Header Processor Voltage Regulator Module 1.260 0.748 Size Project: Document Number 1.244 0.732 Custom 855PM Platform 1.228 0.716 VR Interposer Headers Date: Monday, February 24, 2003 Sheet 1.212 0.700...
  • Page 366 855PM Core and Processor IO VR's (+VCCP) +V5S 9,17,20,21,24,31,32,33,35,36,41 +VDC 18,36,41 +VCCP 3,4,5,7,15,16,17,39 +V1.2S_MCH 7,39 29,34 VR_ON IMVP-IV CORE_VR_ON 36 Title 855PM VR AND VCCP Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 367 IMVP-IV Core VR +V3.3S 5,9,10,14,15,17,18,20,23,28,30,31,32,33,36,41 +V5S 9,17,20,21,24,31,32,33,35,36,41 +VDC 18,36,41 +VCC_CORE 4,39 14,16,34,36 PM_STPCPU# ON_BOARD_VR_ON ON_BOARD_VR_PWRGD 36 IMVP-IV 16,34,36 PM_DPRSLPVR Title IMVP-IV VR Controller Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 368 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 3,4,5,7,15,16,17,37,42 +VCCP 3,4,5,7,15,16,17,37,42 +VCCP Place near 855PM Place near CPU C167 C400 C399 C422 C413 C402 C410 C412 C435 C165 C3900 C171 C395 C401 C406 C393...
  • Page 369 VSENSE_2_D 0.022uF 267_1% 8200pF R484 R258 FSEL 14,16,22,29,34,41 PM_SLP_S3# NO_STUFF_4.99k_1% Vtt Sense Vtt Sense R475 NO_STUFF_0 17,41 DC_SLP_S5# DDR VR DDR VR DDR VR DDR VR Title DDR_VR Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 370 Push button Front Panel MAX6816 RESET +V3.3ALWAYS 5,9,16,17,18,19,20,24,25,26,29,33,34,36 CON72,RCPTL,TH,700000-668.Normal 17,18,19,20,24,34,40 PM_SYSRST# 16 ITP_DBRESET# V5_TURNER 74AHC1G08 R115 0.01_1% +V3.3 7,9,15,17,20,24,27,29,32,34,36,40 V3.3_TURNER R118 0.01_1% 3Pin_RECEPTICLE Title DC/DC Card Connector CON3,RCPTL,TH,700000-667.Normal Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 371 PAGE INTENTIONALLY LEFT BLANK Title DEBUG LOGIC Size Project: Document Number 855PM Platform Date: Monday, February 24, 2003 Sheet...
  • Page 372 PG 40 +V1.25S RST_HDR SMC_RST# MAX809 PG 30 PG 29 +V5A VR PG 18 +V5_ALWAYS INTERPOSER_PRES# ON_BOARD_VR_ON VR_SHUTDOWN 855PM & VCCP_PGD Core VR VCCP VR CORE_VR_ON PG 36 855PM_PGD PG 37 PG 36 PG 36 PG 38 PG 37 ON_BOARD_VR_PWRGD...

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