Decoupling Recommendations; Processor Decoupling Guidelines; Intel 855Pm Mch Decoupling Guidelines; Intel 82801Dbm Ich4-M Decoupling Guidelines - Intel 855PM Design Manual

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11.7.

Decoupling Recommendations

Intel recommends proper design and layout of the system board bulk and high frequency decoupling
capacitor solution to meet the transient tolerances for each component. To meet the component transient
load steps, it is necessary to properly place bulk and high frequency capacitors close to the component
power and ground pins.
11.7.1.

Processor Decoupling Guidelines

See Section 5.9.2 for details on recommended V
11.7.2.

Intel 855PM MCH Decoupling Guidelines

Table 82. Decoupling Requirements for the Intel 855PM MCH

Pin
VCC_MCH
VCC1_5
VCC1_8
VCCGA,
VCCHA
VCCSM
V
CCP
11.7.3.

Intel 82801DBM ICH4-M Decoupling Guidelines

The Intel 82801DBM ICH4-M is capable of generating large current swings when switching between
logic high and logic low. This condition could cause the component voltage rails to drop below
specified limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance
is added in parallel to the voltage input pins. Intel recommends that the developer use the amount of
decoupling capacitors specified in
Table 83 to ensure the component maintains stable supply voltages. The capacitors should be placed as
close to the package as possible (100 mils nominal). Rotate caps that set over power planes so that the
loop inductance is minimized (see Figure 146). The basic theory for minimizing loop inductance is to
consider which voltage is on Layer 2 (power or ground) and spin the decoupling cap with the opposite
voltage towards the BGA (Ball Grid Array). This greatly minimizes the total loop inductance. Intel
recommends that for prototype board designs, the designer should include pads for extra power plane
decoupling caps.
®
Intel 855PM Chipset Platform Design Guide
Decoupling Decoupling Type (Pin type)
Requirements
See Section 5.9.5 Decoupling Cap: See Table 22
See Section 7.3.4 Decoupling Cap: See Section
7.3.4
(2) 0.1 µF Decoupling Cap: See Section 8.5
(2) 10 µF (2) Decoupling Cap: See Section 5.2
10 nF
See Section Decoupling Cap: See Section
11.5.1.1 11.5.1.1
See Section 5.9.4 Decoupling Cap: See Table 21
Platform Power Delivery Guidelines
decoupling solutions.
CC-CORE
Decoupling Placement
Place near balls: See Figure 69
Place near balls: See Section
7.3.4
Place near balls: See Section 8.5
Place near balls: T13, T17; See
Section 5.2
Place near balls: See Section
11.5.1
Place near balls: See Figure 64 &
Figure 66
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