Processor Fsb Strapping; Figure 38. Intel 855Pm Mch Hswng[1:0] Layout - Intel 855PM Design Manual

R
example below is done by means of a via to Layer 6 and a short trace from the via to the dog bone via of
HSWNG[1:0] pin as illustrated on the right side of Figure 38.

Figure 38. Intel 855PM MCH HSWNG[1:0] Layout

HSWNG1
4.1.9.

Processor FSB Strapping

The Intel Pentium M processor / Intel Celeron M processor and Intel 855PM MCH both have pins that
require termination for proper component operation.
1. For the processor, a stuffing option should be provided for the TEST[3:1] pins to allow a 1-k ±
5% pull-down to ground for testing purposes. For proper processor operation, the resistor should
not be stuffed. Resistors for the stuffing option on these pins should be placed within 2.0 inches of
the processor. Figure 39 illustrates the recommended layout for the stuffing options. For normal
operation, these resistors should not be stuffed.
2. For the MCH, the ST[1] signal does not require an external pull-up for normal operation. This
signal has an internal pull-up that straps the FSB for 100-MHz operation. However, a stuffing
option for a 1-k ± 5% pull-up to a 1.5-V source can be provided for testing purposes. For details
on the ST[0] signal, refer to Section 6.3.
3. The processor's ITP signals, TDI, TMS, TRST and TCK should assume default logic values even
if the ITP debug port is not used. The TDO signal may be left open or no connect in this case.
Table 16 summarizes the default strapping resistors for these signals. These resistors should be
connected to the processor within 2.0 inches from their respective pins. It is important to note that
Table 16 is applicable only when neither the onboard ITP nor ITP interposer are planned to be
used. See Section 4.2 on cautions against designs with lack of debug tools support. Intel does not
recommend use of the ITP interposer debug port if there is a dependence only on the motherboard
termination resistors. The signals below should be isolated from the motherboard via specific
termination resistors on the ITP interposer itself per interposer debug port recommendations. For
the case where the onboard ITP700FLEX debug port is used refer to Section 4.3 for default
termination recommendations.
®
Intel 855PM Chipset Platform Design Guide
C1b
R2b
C1a
R1b
R2a
R1a
SECONDARY SIDE
HSWNG0
L6
FSB Design Guidelines
73