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the Vcc1_5 and Vcc3_3 power pins. Also, the LAN_RST# pin of the ICH4-M should be pulled-down to
GND with a 10-k resistor to keep the interface disabled.
9.9.5.
Design and Layout Consideration for Intel 82540EP / 82551QM
For specific design and layout considerations for the Intel 82540EP Gigabit Ethernet Controller and the
Intel 82551QM Faster Ethernet Controller, please refer to the following documents:
82551QM / 82540EM Interchangeable LOM Design Application Note (AP 432) (Reference
#10565)
82540EP Gigabit Ethernet Controller Networking Silicon Product Preview Datasheet
82540EP Gigabit Ethernet Controller Specification Update
82540EP/82541EI & 82562EZ(EX) Dual Footprint Design Guide Application Note (AP-444)
(Reference# 12504)
9.9.6.
General Intel 82562ET / 82562EM / 82551QM / 82540EP
Differential Pair Trace Routing Considerations
Trace routing considerations are important to minimize the effects of crosstalk and propagation delays
on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible
to decrease interference from other signals, including those propagated through power and ground
planes.
Observe the following suggestions to help optimize board performance.
Note: Some suggestions are specific to a 4.3-mil stack-up.
Maintain constant symmetry and spacing between the traces within a differential pair.
Keep the signal trace lengths of a differential pair equal to each other.
Keep the total length of each differential pair under 4 inches. (Many customer designs with
differential traces longer than 5 inches have had one or more of the following issues: IEEE phy
conformance failures, excessive EMI (Electro Magnetic Interference), and/or degraded receive
BER (Bit Error Rate).)
Do not route the transmit differential traces closer than 100 mils to the receive differential traces.
Do not route any other signal traces both parallel to the differential traces, and closer than 100 mils
to the differential traces (300 mils is recommended).
Keep maximum separation between differential pairs to 7 mils.
For high-speed signals, the number of corners and vias should be kept to a minimum. If a 90° bend
is required, Intel recommends using two 45° bends instead. Refer to Figure 124.
Traces should be routed away from board edges by a distance greater than the trace height above
the ground plane. This allows the field around the trace to couple more easily to the ground plane
rather than to adjacent wires or boards.
Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from the
clock. And as a general rule, place traces from clocks and drives at a minimum distance from
apertures by a distance that is greater than the largest aperture dimension.
®
Intel
855PM Chipset Platform Design Guide
I/O Subsystem
221
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