Figure 71. V Secondary Layer Decoupling Capacitor Placement (Zoom In View) - Intel 855PM Design Manual

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Figure 71 further illustrates a "Zoom In View" of the secondary side layout that was shown on the
bottom left side of Figure 70. Notice the specific locations of the 0805, 2.2-µF mid frequency capacitor
and the 0603 form factor 10 nF, 15 nF, 22 nF, 47 nF, and 220 nF high frequency decoupling capacitors.
The 0603 capacitors' V
vias. All these capacitors are shorted with the V
vias of the pin field and the two extra vias that were added to effectively stitch the primary side, Layer 5,
Layer 6, and the secondary side V
0603 form factor 10 nF, 15 nF, 22 nF, 47 nF, and 220 nF capacitors connect to a ground ring on the
secondary side and a stitching ground via is placed within 45 mils of the ground pad of the capacitor.
On the top left corner of Figure 71 four pairs of the V
and ground floods for the two 150-µF bulk decoupling POSCAPs to internal layers. The V
MCH
vias are offset 25 x 25 mils in the X and Y directions from the ground vias. This cluster of vias is placed
symmetrically under the middle of the body of the POSCAPs.
Figure 71. V Secondary Layer Decoupling Capacitor Placement (Zoom in View)
CC-MCH
2x150µF
1.5v
1.8v
®
Intel 855PM Chipset Platform Design Guide
side pads are placed within 45 mils of their respective row of V
CC-MCH
floods to the decoupling capacitors. The groundside of the
CC-MCH
25mil
25mil
0805
2.2µF
Extra Via
0603
22nF
0603 0603
10nF 47nF
2.5v
Platform Power Requirements
flood on the secondary side plane to the V
CC-MCH
and ground vias connect the two small V
CC-MCH
Secondary
Side
1.2v
Extra Via
45mil
0603 0603
15nF 220nF
CC-MCH
CC-MCH
CC-
CC-MCH
1.05v
45mil
123