Gpio - Intel 855PM Design Manual

Chipset platform for use with pentium m and celeron m processors
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Platform Design Checklist
14.8.2.

GPIO

Checklist Items
GPIO[7] & [5:0]:
GPIO Balls
These balls are in the Main Power Well. Pull-ups must use
the V
Unused core well inputs must be pulled up to V
GPIO[1:0] can be used as REQ[B:A]#.
GPIO[1] can be used as PCI REQ[5]#.
GPIO[5:2] can be used as PIRQ[H:E]#.
These signals are 5-V tolerant
These pins are inputs
GPIO[8] & [13:11]:
These balls are in the Resume Power Well. Pull-ups go to
V
Unused resume well inputs must be pulled up to V
These are the only GPIs that can be used as ACPI
compliant wake events.
These signals are not 5-V tolerant.
GPIO[8] can be used as SMC_EXTSMI#
GPIO[11] can be used as SMBALERT#.
GPIO[13] can be used as SMC_WAKE_SCI#
These pins are inputs
GPIO[23:16]:
Fixed as output only. Can be left NC.
In Main Power Well (V
GPIO[17:16] can be used as GNT[B:A]#.
GPIO[17] can be used as PCI GNT[5]#.
STP_PCI#/GPIO[18] – used in mobile as STP_PCI# only.
SLP_S1#/GPIO[19] – used in mobile as SLP_S1# only.
STP_CPU#/GPIO[20] – used in mobile as STP_CPU# only.
C3_STAT#/GPIO[21] – used in mobile as C3_STAT# only.
CPUPERF#/GPIO[22] – open drain signal. Used in mobile
as CPUPERF# only.
SSMUXSEL/GPIO[23] – used in mobile as SSMUXSEL only.
GPIO[28,27,25,24]:
I/O balls. Default as outputs. Can be left NC.
These pins are in the Resume Power Well
CLKRUN#/GPIO[24] (Note: use pull up to V
required to be pulled up)
GPIO[28, 27, 25] From resume power well (V
(Note: use pull up to V
These signals are NOT 5-V tolerant.
GPIO[25] can be used as AUDIO_PWRDN
308
Recommendations
3_3 plane.
CC
Sus3_3 plane.
CC
3_3).
CC
3_3 if this signal is pulled up)
CC
Ensure ALL unconnected signals are
OUTPUTS ONLY!
3_3.
CC
Main power well GPIOs are 5-V tolerant,
except for GPIO[43:32]. Resume power
well GPIOs are not 5-V tolerant
Sus3_3.
CC
3_3 if signal is
CC
Sus3_3).
CC
®
Intel
855PM Chipset Platform Design Guide
R
Reason/Impact

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