Intel 80960KB Manual

EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
High-Performance Embedded
Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at
25 MHz
512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
4 Gigabyte, Linear Address Space
Pin Compatible with 80960KA
FOUR
SIXTEEN
80-BIT FP
32-BIT GLOBAL
REGISTERS
REGISTERS
80-BIT
FPU
512-BYTE
INSTRUCTION
INSTRUCTION
FETCH UNIT
CACHE
Figure 1. The 80960KB Processor's Highly Parallel Architecture
© INTEL CORPORATION, 2004
80960KB
Built-in Interrupt Controller
— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz
Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
132-Lead Packages:
— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)
On-Chip Floating Point Unit
— Supports IEEE 754 Floating Point
— Four 80-Bit Registers
— 13.6 Million Whetstones/s (Single
64- BY 32-BIT
32-BIT
LOCAL
INSTRUCTION
REGISTER
EXECUTION
CACHE
UNIT
MICRO-
INSTRUCTION
INSTRUCTION
DECODER
SEQUENCER
August, 2004
Standard
Precision) at 25 MHz
32-BIT
BUS CONTROL
LOGIC
MICRO-
INSTRUCTION
ROM
Order Number: 270565-008
80960KB
32-BIT
BURST
BUS