Figure 39. Processor Strapping Resistor Layout; Table 16. Itp Signal Default Strapping When Itp Debug Port Not Used - Intel 855PM Design Manual

FSB Design Guidelines

Table 16. ITP Signal Default Strapping When ITP Debug Port Not Used

Signal
TDI
TMS
TRST#
TCK
TDO
Figure 39 illustrates the recommended layout for the processor's strapping resistors. To avoid
interaction with FSB routing, the TEST[3:1] signal resistors are placed on the secondary side of the
motherboard. To avoid GND via interaction with the FSB routing, the resistors share GND via
connections with the A8, A17, and A20 ground pins of the processor.
The 150- pull-up resistor to V
board. The placement of the strapping resistors for TDI, TMS, TRST#, and TCK is not critical.

Figure 39. Processor Strapping Resistor Layout

TEST[2]
74
Resistor Value Connect To
± V
150 5%
CCP
± V
39 5%
CCP
±
GND
680 5%
±
GND
27 5%
Open NC
(1.05 V) for TDI is shown in Figure 39 on the secondary side of the
CCP
SECONDARY SIDE
A8, A17 & A20
GND
Pins
TEST[3]
Resistor Placement
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
N/A
TDI
TMS
TRST#
TCK
®
Intel 855PM Chipset Platform Design Guide
R
TEST[1]