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4.1.8.
AGTL+ I/O Buffer Compensation
The processor has four pins, COMP[3:0], and the Intel 855PM MCH has two pins, HRCOMP[1:0], that
require compensation resistors to adjust the AGTL+ I/O buffer characteristics to specific board and
operating environment characteristics. Also, the MCH requires two special reference voltage generation
circuits to pins HSWNG[1:0] for the same purpose described above. Refer to the Intel
Processor Datasheet, Intel
process with 2-MB L2 Cache Datasheet, and Intel
DDR200/266MHz Datasheet for details on resistive compensation.
4.1.8.1.
Processor AGTL+ I/O Buffer Compensation
For the processor, the COMP[2] and COMP[0] pins must each be pulled-down to ground with 27.4
1% resistors and should be connected to the processor with a Zo = 27.4
inches from the processor pins. The COMP[3] and COMP[1] pins must each be pulled-down to ground
with 54.9
than 0.5 inches from the processor pins.. COMP[3:0] traces should be at least 25 mils (> 50 mils
preferred) away from any other toggling signal.
The recommended layout of the processor COMP[3:0] resistors is illustrated in Figure 33. To avoid
interaction with FSB routing on internal layers and VCCA power delivery on the primary side, Layer 1,
COMP[1:0] resistors are placed on the secondary side. Ground connections to the COMP[1:0] resistors
use a small ground flood on the secondary side layer and connect only with a single GND via to stitch
the GND planes. The compact layout as shown in Figure 33 should be used to avoid excessive
"perforation" of the V
with an ~18-mil wide (Zo = 27.4 ) and 160-mil long trace to COMP0. Necking down to 14 mils is
allowed for a short length to pass in between the dog bones. The 54.9- resistor connects with a regular
5-mil wide (Zo = 55 ) and 267-mil long trace to COMP1.
Placement of COMP[1:0] on the primary side is possible as well. An alternative placement
implementation is shown if Figure 34.
To minimize motherboard space usage and produce a robust connection, the COMP[3:2] resistors are
also placed on the secondary side (Figure 33, right side). A 27.4- resistor connects with an 18-mil
wide (Zo = 27.4 ) and 260-mil long trace to COMP2. Necking down to 14 mils is allowed for a short
length to pass in between the dog bones. Notice that the COMP2 (Figure 33, left side) dog bone trace
connection on the primary side is also widened to 14 mils to meet the Zo = 27.4- characteristic
impedance target. The right side of Figure 33 also illustrates how the 54.9
a regular 5-mil wide (Zo = 55 ) and 100-mil long trace to COMP3. The ground connection of
COMP[3:2] is done with a small flood plane on the secondary side that connects to the GND vias of
pins AA1 and Y2 of the processor pin-map. This is done to avoid via interaction with the FSB routing
on Layer 3 and Layer 6.
For COMP2 and COMP0, it is extremely important that 18-mil wide dog bone connections on the
primary side and 18-mil wide traces on the secondary sides be used to connect the signals to
compensation resistors on the secondary side. The use of 18-mil wide dog bones and traces is used to
achieve the Zo = 27.4
®
Intel
855PM Chipset Platform Design Guide
®
Celeron M Processor Datasheet, Intel® Pentium® M Processor on 90nm
± 1% resistors and should be connected to the processor with a Zo = 55
plane power delivery. Figure 33 illustrates how a 27.4- resistor connects
CCP
target to ensure proper operation of the FSB. See Figure 35 for more details.
®
855PM Memory Controller Hub (MCH)
trace that is less than 0.5
± 1% resistor connects with
FSB Design Guidelines
®
Pentium M
±
trace that is less
69
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