Intel 855PM Design Manual page 344

Chipset platform for use with pentium m and celeron m processors
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A
19,20,21
PCI_AD[31:0]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
4
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
3
PCI_AD31
19,20,21
PCI_C/BE0#
19,20,21
PCI_C/BE1#
19,20,21
PCI_C/BE2#
19,20,21
PCI_C/BE3#
TP_GNT0#
19
PCI_GNT1#
19
PCI_GNT2#
20
PCI_GNT3#
21
PCI_GNT4#
18
PCI_REQ0#
18,19
PCI_REQ1#
18,19
PCI_REQ2#
18,20
PCI_REQ3#
18,21
PCI_REQ4#
14
CLK_ICHPCI
18,19,20,21
PCI_DEVSEL#
18,19,20,21
PCI_FRAME#
19
PCI_REQA#
2
21
PCI_REQB#
16,19
PCI_GNTA#
21
PCI_GNTB#
18,19,20,21
PCI_IRDY#
19,20,21
PCI_PAR
18,19,20
PCI_PERR#
18,19,20,21
PCI_LOCK#
W2
18,19,20,21
PCI_SERR#
18,19,20,21
PCI_STOP#
18,19,20,21
PCI_TRDY#
ICH_PME#
R297
9,19,20,34
PCI_PME#
6,23,28,34,42
PCI_RST#
1
9,19,20,21,29,30,31,34
BUF_PCI_RST#
U41
BUFFER
A
B
U42A
SM_INTRUDER#
H5
PCI_AD0
SMLINK0
J3
PCI_AD1
SMLINK1
H3
PCI_AD2
SMB_CLK
K1
PCI_AD3
SMB_DATA
G5
PCI_AD4
SMB_ALERT#/GPIO11
J4
PCI_AD5
H4
PCI_AD6
CPU_A20GATE
J5
PCI_AD7
CPU_A20M#
K2
ICH4-M
PCI_AD8
CPU_DPSLP#
G2
PCI_AD9
CPU_FERR#
L1
PCI_AD10
CPU_IGNNE#
PART A
G4
PCI_AD11
CPU_INIT#
L2
PCI_AD12
CPU_INTR
H2
PCI_AD13
CPU_NMI
L3
PCI_AD14
CPU_PWRGOOD
F5
PCI_AD15
CPU_RCIN#
F4
PCI_AD16
CPU_SLP#
N1
PCI_AD17
CPU_SMI#
E5
PCI_AD18
CPU_STPCLK#
N2
PCI_AD19
E3
PCI_AD20
HUB_PD0
N3
PCI_AD21
HUB_PD1
E4
PCI_AD22
HUB_PD2
M5
PCI_AD23
HUB_PD3
E2
PCI_AD24
HUB_PD4
P1
PCI_AD25
HUB_PD5
E1
PCI_AD26
HUB_PD6
P2
PCI_AD27
HUB_PD7
D3
PCI_AD28
HUB_PD8
R1
PCI_AD29
HUB_PD9
PCI
D2
PCI_AD30
HUB_PD10
P4
I/F
PCI_AD31
HUB_PD11
HUB_CLK
J2
PCI_C/BE0#
K4
PCI_C/BE1#
HUB_PSTRB#
M4
PCI_C/BE2#
HUB_PSTRB
N4
HUB_RCOMP
PCI_C/BE3#
HUB_VREF
C1
PCI_GNT0#
HUB_VSWING
E6
PCI_GNT1#
A7
PCI_GNT2#
INT_APICCLK
B7
PCI_GNT3#
INT_APICD0
D6
PCI_GNT4#
INT_APICD1
INT_PIRQA#
B1
PCI_REQ0#
INT_PIRQB#
A2
PCI_REQ1#
INT_PIRQC#
B3
PCI_REQ2#
INT_PIRQD#
C7
PCI_REQ3#
INT_PIRQE#/GPIO2
B6
PCI_REQ4#
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
P5
PCI_CLK
INT_PIRQH#/GPIO5
M3
PCI_DEVSEL#
INT_IRQ14
F1
PCI_FRAME#
INT_IRQ15
B5
PCI_GPIO0/REQA#
INT_SERIRQ
A6
PCI_GPIO1/REQB_L/REQ5#
E8
PCI_GPIO16/GNTA#
EEP_CS
C5
PCI_GPIO17/GNTB_L/GNT5#
EEP_DIN
L5
PCI_IRDY#
EEP_DOUT
G1
PCI_PAR
EEP_SHCLK
L4
PCI_PERR#
M2
PCI_LOCK#
LAN_RXD0
PCI_PME#
LAN_RXD1
U5
PCI_RST#
LAN_RXD2
K5
PCI_SERR#
LAN_TXD0
F3
PCI_STOP#
LAN_TXD1
F2
PCI_TRDY#
LAN_TXD2
LAN_JCLK
LAN_RSTSYNC
LAN_RST#
ICH4-M
0
INT_APICCLK
INT_APICD0
INT_APICD1
+V3.3
7,9,17,20,24,27,29,32,34,36,40,41
5
2
4
1
OE
3
B
C
3,4,5,7,16,17,37,39,42
+VCCP
W6
SM_INTRUDER# 18,34
AC3
SMLINK0 18,19,20
AB1
SMLINK1 18,19,20
AC4
SMB_CLK 10,14,18,21
AB4
SMB_DATA 10,14,18,21
AA5
SMB_ALERT# 18,34
Y22
CPU_A20M#
R521
0
AB23
CPU_DPSLP#
R299
0
U23
CPU_FERR#
R518
56
AA21
CPU_IGNNE#
R513
0
W21
CPU_INIT#
V22
CPU_INTR
R517
0
AB22
CPU_NMI
R298
0
V21
Y23
U22
CPU_SLP#
R510
0
U21
CPU_SMI#
R296
0
W23
CPU_STPCLK#
R512
0
V23
HUB_PD[10:0] 6,8
HUB_PD0
L19
HUB_PD1
L20
HUB_PD2
M19
HUB_PD3
M21
HUB_PD4
PLACE RCOMP resistor
P19
HUB_PD5
R19
within 0.5" of ICH pad using
HUB_PD6
T20
a thick trace
HUB_PD7
R20
HUB_PD8
RCOMP R should be 2/3
P23
HUB_PD9
L22
board impedance
HUB_PD10
N22
K21
TP_HUB_PD11 34
T21
CLK_ICH66 8,14
N20
HUB_PSTRB# 6,8
P21
HUB_PSTRB 6,8
HUB_RCOMP_ICH
R23
HUB_VREF_ICH
M23
HUB_VSWING_ICH
R22
INT_APICCLK
J19
INT_APICD0
H19
INT_APICD1
K20
D5
INT_PIRQA# 9,18,19,20,21
C2
INT_PIRQB# 9,18,19,20,21
B4
INT_PIRQC# 18,19,20,21
A3
INT_PIRQD# 18,19,20,21
INT_PIRQE#_D
R198
0
C8
INT_PIRQE# 18,20
INT_PIRQF#_D
R197
0
D7
INT_PIRQF# 18,20
INT_PIRQG#_D
R160
0
C3
INT_PIRQG# 18,20
INT_PIRQH#_D
R219
0
C4
INT_PIRQH# 18,20,34
AC13
INT_IRQ14 18,23,34
17
+V3.3_ICHLAN
AA19
INT_IRQ15 18,23,34
J22
INT_SERIRQ 19,20,21,29,31,34
U35
EEP_CS
D10
1
CS
VCC
EEP_SK
D11
2
SK
DC
A8
3
DI
ORG
EEP_DIN
C12
4
DO
GND
A10
LAN_RXD0 27
A9
LAN_RXD1 27
EEPROM for ICH4-M LAN
A11
LAN_RXD2 27
B10
LAN_TXD0 27
C10
LAN_TXD1 27
LAN_EEP_DOUT 16
A12
LAN_TXD2 27
C11
LAN_JCLK 27
B11
LAN_RST 27
Y5
PM_LANPWROK 27,29
R483
R498
R494
10K
10K
0
C
D
5,9,10,14,17,18,20,23,28,30,31,32,33,36,37,38,41,42
R520
56
H_A20GATE 33
H_A20M# 3
H_DPSLP# 3,6,34
H_FERR# 3
H_IGNNE# 3
R300
H_INIT#_D
330
H_INTR 3,34
H_NMI 3,34
H_PWRGD 3,34
R301
0
H_RCIN# 29,34
H_INIT# 3,34
H_CPUSLP# 3,34
H_SMI# 3,34
H_STPCLK# 3,34
J61
1
2
3
R276
36.5
NO_STUFF_CON3_HDR
1%
2
J63
C518
R464
0.01UF
10 mil trace, 7 mil space
+V1.8S_ICHHUB 17
R264
150_1%
(1/2) 1.8V
range for R264, R267: 100 - 150 ohm
C300
0.01UF
R267
150_1%
No Stuff
8
TP_EEPROM0
7
TP_EEPROM1
6
5
Title
ICH4-M (1 of 3)
Size
Project:
A
855PM Platform
Date:
Monday, February 24, 2003
D
E
+V3.3S
R246
R249
1.5K
330
6
FWH_INIT# 28
CR11B
2
3904
4
1
3
CR11A
5
3904
4
17
+V1.8S_ICHHUB
R465
150_1%
HUB_VREF_ICH_D
1
No Stuff
R490
0
C506
150_1%
3
0.01UF
HUB INTERFACE VSWING VOLTAGE
HUB INTERFACE LAYOUT:
Route signals with 4/8 trace/space routing. Signals
must match +/- 0.1" of HUB_PSTRB/PSTRB#
J60
2
1
Document Number
Rev
Sheet
15
of
47
E

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