Intel 855PM Design Manual page 5

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5.7. Voltage Regulator Topology ........................................................................................100
5.8. Voltage Regulator Design Recommendations ............................................................100
5.8.1.
5.8.2.
5.8.3.
5.8.4.
5.8.5.
5.9. Processor Decoupling Recommendations ..................................................................104
5.9.1.
5.9.2.
5.9.3.
5.9.4.
5.9.5.
6. System Memory Design Guidelines (DDR-SDRAM)................................................................125
6.1. DDR 200/266/333 MHz System Memory Topology and Layout Design Guidelines ...126
6.1.1.
6.1.2.
6.1.3.
6.1.4.
6.1.5.
6.1.6.
6.1.7.
6.2. Intel 855PM MCH DDR Signal Package Lengths .......................................................160
®
Intel 855PM Chipset Platform Design Guide
High Current Path, Top MOSFET Turned ON .............................................101
High Current Paths During Abrupt Load Current Changes .........................101
High Current Paths During Switching Dead Time........................................102
High Current Path with Bottom MOSFET(s) Turned ON .............................102
General Layout Recommendations .............................................................103
Transient Response .....................................................................................104
High Frequency, Mid Frequency, and Bulk Decoupling...............................105
Processor Core Voltage Plane and Decoupling ..........................................106
Intel Pentium M Processor / Intel Celeron M Processor
and Intel 855PM MCH V
5.9.4.1. Processor V
CCP
5.9.4.2. Intel 855PM MCH V
Intel 855PM MCH Core Voltage Plane and Decoupling ..............................119
Data Signals - SDQ[71:0], SDQS[8:0].........................................................126
6.1.1.1. Data to Strobe Length Matching Requirements............................129
6.1.1.2. Strobe to Clock Length Matching Requirements ..........................131
6.1.1.3. Data Routing Example ..................................................................133
6.1.1.4. Support for Small Form Factor Design DDR Data Bus Routing ...134
Control Signals - SCKE[3:0], SCS#[3:0] .....................................................134
6.1.2.1. Control to Clock Length Matching Requirements .........................136
6.1.2.2. Control Routing Example ..............................................................138
Command Signals - SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#...........139
6.1.3.1. Command Topology 1 Solution.....................................................139
6.1.3.1.1. Routing Description for Command Topology 1...........139
6.1.3.1.2. Command Topology 1 to Clock Length Matching
Requirements..............................................................141
6.1.3.1.3. Command Topology 1 Routing Example ....................143
6.1.3.2. Command Topology 2 Solution.....................................................144
6.1.3.2.1. Routing Description for Command Topology 2...........144
6.1.3.2.2. Command Topology 2 to Clock Length Matching
Requirements..............................................................146
6.1.3.2.3. Command Topology 2 Routing Example ....................148
Clock Signals - SCK[5:0], SCK#[5:0] ..........................................................149
6.1.4.1. Clock Signal Length Matching Requirements...............................151
6.1.4.1.1. Clock Routing Example...............................................154
6.1.4.2. Intel 855PM Chipset High Density Memory Support ....................155
Feedback - RCVENOUT#, RCVENIN#.......................................................155
6.1.5.1. RCVEN# Routing Example ...........................................................156
Support for "DDP Stacked" SO-DIMM Modules ..........................................157
Recommended Design Option to Support PC2700 DDR SDRAM
with Existing PC1600 and PC2100 Intel 855PM Platforms .........................158
6.1.7.1. Shortened Data Signal Group Trace Length ................................158
6.1.7.1.1. Supporting PC2700 Based on an Existing PC Platform
Layout .........................................................................158
6.1.7.1.2. Additional Design Considerations for Adapting Intel
855PM DDR 200/266 MHz Platforms To Support
PC2700 .......................................................................159
Voltage Plane and Decoupling........................114
CCP
Voltage Plane and Decoupling............................114
Voltage Plane and Decoupling................118
CCP
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