Clock Checklist; Resistor Recommendations - Intel 855PM Design Manual

Platform Design Checklist
14.5. CK-408 Clock Checklist
14.5.1.

Resistor Recommendations

Pin Name
Pull up/Pull down
3V66[5:0]
CPU[0], CPU[0]# Pull down to GND
CPU[1], CPU[1]#
CPU[2], CPU[2]#
CPU_STOP#
DOT
IREF Pull down to GND
MULT[0] Pull up to Vcc3_3
PCI[6:0]
PCI_STOP#
PCIF[2:0]
PWRDWN#
290
CK-408 Clock – Resistor Recommendations
System
49.9 ± 1%
475 ± 1%
10 k
Series Resistor
(
33 Use three clock signals for MCH, ICH4-M,
and AGP controller.
See Section 10.2.2 for MCH and ICH4-M
CLK66 routing requirements.
33 It is required to connect one CPU clock
pair to processor and another pair to MCH.
See Section 12.2.1 for further discussion.
If ITP700FLEX Is Used:
rd
Route 3 CPU clock pair to ITP700FLEX
(Routing to CPU socket NOT necessary).
See Section 4.3.1.3 for routing
requirements.
If ITP Interposer Is Used:
rd
Route 3 CPU clock pair to the ITP_CLK
signals of the CPU socket (Routing to
ITP700FLEX NOT necessary).
Point to point connection to the ICH4-M's
STP_CPU# signal.
33 If the signal is used, one 33 series
resistor is required for each receiver.
If NOT used, this signal can be left as NC
(No Connect).
33 If the signal is used, one 33
resistor is required for each receiver.
If NOT used, this signal can be left as NC
(No Connect).
See Section 10.2.5 for routing
requirements.
Point to point connection to the ICH4-M's
STP_PCI# signal.
33 Use one free running PCI clock signal for
the ICH4-M.
If NOT used, this signal can be left as NC
(No Connect).
See 10.2.4 for routing requirements.
If S1M Is Supported:
This signal should be driven by the logical
AND of the ICH4-M's SLP_S1# and
SLP_S3# signals. See Figure 152.
If S1M Is NOT Supported but S3 is
supported:
®
Intel 855PM Chipset Platform Design Guide
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Notes
series