Data To Strobe Length Matching Requirements; Table 25. Sdq[71:0] To Sdqs[8:0] Length Mismatch Mapping - Intel 855PM Design Manual

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6.1.1.1.

Data to Strobe Length Matching Requirements

The data and check bit signals, SDQ[71:0], are grouped by byte lanes and associated with a data strobe,
SDQS[8:0]. The data signals and check bit signals must be length matched to their associated strobe
within ± 25 mils provided that individual trace lengths (i.e. L1, L2, and L3) specifications are not
violated. For SO-DIMM0 this length matching includes the motherboard trace length to the pads of the
SO-DIMM0 connector (L1 + Rs Length + L2). For SO-DIMM1, the motherboard trace length to the
pads of the SO-DIMM1 connector (L1 + Rs Length + L2 + L3).
For associated SDQS Length = X and SDQ Byte Group Length = Y, the following must be met:
No length matching is required from the SO-DIMM1 to the parallel termination resistors. Table 25 and
Figure 73 below depict the length matching requirements between the DQ, CB, and DQS signals.

Table 25. SDQ[71:0] to SDQS[8:0] Length Mismatch Mapping

Signal
SDQ[7:0]
SDQ[15:8]
SDQ[23:16]
SDQ[31:24]
SDQ[39:32]
SDQ[56:40]
SDQ[55:48]
SDQ[63:56]
SDQ[71:64]
Note: The recommended individual trace lengths (i.e. L1, L2, and L3) specifications can not be violated when
the signal lengths are tolerance by ± 25 mils.
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Intel 855PM Chipset Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
( X – 25 mils ) Y ( X + 25 mils )
Mismatch Relative To
± 25 mils SDQS0
± 25 mils SDQS1
± 25 mils SDQS2
± 25 mils SDQS3
± 25 mils SDQS4
± 25 mils SDQS5
± 25 mils SDQS6
± 25 mils SDQS7
± 25 mils SDQS8
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