Topology 2B: Cmos Signals Driven By Intel 82801Dbm Ich4-M - Dpslp; Figure 20. Routing Illustration For Topology 2B; Table 12. Layout Recommendations For Topology 2B - Intel 855PM Design Manual

FSB Design Guidelines
4.1.4.1.5. Topology 2B: CMOS Signals Driven by Intel 82801DBM ICH4-M – DPSLP#
The Topology 2B CMOS DPSLP# signal driven by the Intel 82801DBM ICH4-M ( processor CMOS
signal input) should adhere to the following routing and layout recommendations illustrated in Figure
20. As listed in Table 12, the L1 and L2 segments of the DPSLP# signal topology can be routed as either
micro-strip or strip-lines using 55
DPSLP# signal should be routed point-to-point with the daisy chain topology shown. The routing of
DPSLP# at the processor should fork out to both the ICH4-M and the Intel 855PM MCH. Segments L1
and L2 from Figure 20 should not T-split from a trace from the processor pin.

Figure 20. Routing Illustration for Topology 2B

Table 12. Layout Recommendations for Topology 2B

L1
0.5" – 12.0"
0.5" – 12.0"
Figure 21 illustrates a DPSLP# signal routing example to conform to Topology 2B recommendations.
The routing starts from the ICH4-M's DPSLP# signal on the secondary side layer of the motherboard to
the processor 's DPSLP# pin. The dog bone via allows switching of the routing layer to Layer 6 thereby
allowing routing to the Intel 855PM MCH's DPSLP# pin located in the same cluster as the remaining
common clock signals routed between the processor and MCH. The routing layer change from the
secondary side to Layer 6 using the processor DPSLP# pin dog bone via is strongly advised to avoid any
stub tapering of the CPU connection off of the ICH4-M to MCH connection to minimize transmission
line effects.
56
± 15% characteristic trace impedance. Note that the ICH4-M's
Intel 855PM
MCH
L2
L2
0.5" – 6.5"
0.5" – 6.5"
Intel
Pentium M
processor
L1
Transmission Line Type
Micro-strip
Strip-line
®
Intel 855PM Chipset Platform Design Guide
R
Intel
ICH4-M