Table 72. Timing Sequence Parameters For Figure 140 - Intel 855PM Design Manual

Platform Power Delivery Guidelines

Table 72. Timing Sequence Parameters for Figure 140

Sym
T173
T175b
T176
T177
T178
T181
T182/T183
T183a
T183b
T184
T185
T186
NOTES:
If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
1.
RTCRST# and the RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.
These transitions are clocked off the internal RTC. One RTC clock is approximately 32 µs.
2.
This transition is clocked off the 66-MHz CLK66. One CLK66 is approximately 15 ns.
3.
250
Description
VccSus supplies active to
RSMRST# inactive
VccLAN supplies active to
LAN_RST# active
Vcc supplies active to PWROK,
VGATE active
PWROK and VGATE active and
SYS_RESET# inactive to
SUS_STAT# inactive
SUS_STAT# inactive to PCIRST#
inactive
VccSus active to SLP_S5#,
SUS_STAT# and PCIRST# active
RSMRST# inactive to SUSCLK
running, SLP_S5# inactive
SLP_S5# inactive to SLP_S4#
inactive
SLP_S4# inactive to SLP_S3#
inactive
Vcc active to STPCLK#,
CPUSLP#, STP_CPU#,
STP_PCI#, SLP_S1#, C3_STAT#
inactive, and CPU Frequency
Strap signals high
PWROK and VGATE active and
SYS_RESET# inactive to
SUS_STAT# inactive and CPU
Frequency Straps latched to strap
values
CPU Reset Complete to
Frequency Straps signals
unlatched from strap values
Min Max Units
5 - ms
10 - ms
10 - ms
32 38 RTCCLK
1 3 RTCCLK
50 ns
110 ms
1 2 RTCCLK
1 2 RTCCLK
50 ns
32 38 RTCCLK
7 9 CLK66
®
Intel 855PM Chipset Platform Design Guide
R
Notes Fig
139
139
139
139
139
139
1 139
139
139
139
2 139
3 139