Figure 136. Pciclk Group To Pci Slot Topology; Table 68. Pciclk Group Routing Guidelines - Intel 855PM Design Manual

R

Figure 136. PCICLK Group to PCI Slot Topology

Clock
Driver

Table 68. PCICLK Group Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Trace Width
Trace to Space Ratio
Group Spacing
Trace Length – A
Trace Length – B
Trace Length – C
Series Termination Resistor (R1)
Skew Requirements
NOTE: Recommended resistor values and trace lengths may change in a later revision of the design guide.
®
Intel 855PM Chipset Platform Design Guide
R1
A
Parameter
Platform Clock Routing Guidelines
B
PCI
Connector
Routing Guidelines
PCICLK
Point-to-Point
Ground Referenced (Contiguous over entire
length)
55 ± 15%
5 mils
1:2 (e.g. 5 mils trace 10 mils space)
Isolation spacing from non-Clock signals =
10 mils minimum
Must be exactly trace length matched to
CLK33 Trace A
(CLK33 Trace B) – 2.5"
Routed 2.5" per the PCI Specification
33 ± 5%
Maximum of ± 1 ns of skew between clocks
within the PCICLK group and a maximum of
± 1 ns of skew between the clocks of this
group and those of CLK33
C
Trace on PCI
Card
PCI Device
Figure Notes
1
Figure 136
Figure 136
Figure 136
Figure 136
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