Processor Reset# Routing Example; Figure 27. Processor Reset# Signal Routing Example With Itp700Flex Debug Port; Table 15. Processor Reset# Signal Routing Guidelines With Itp700Flex Connector - Intel 855PM Design Manual

FSB Design Guidelines

Table 15. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector

L1
1.0" – 6.0"
4.1.5.1.

Processor RESET# Routing Example

Figure 27 illustrates a board routing example for the RESET# signal with an ITP700FLEX debug port
implemented. Figure 27 illustrates how the CPURST# pin of Intel 855PM MCH forks out into two
branches on Layer 6 of the motherboard. One branch is routed directly to the processor's RESET# pin
amongst the rest of the common clock signals. Another branch routes below the address signals and vias
down to the secondary side that route to the Rs and Rtt resistors. These resistors are placed in the
vicinity of the ITP700FLEX debug port. Note the placement of Rs and Rtt next to each other to
minimize the routing between Rs and Rtt as well as the minimal routing between Rs and the
ITP700FLEX connector. Also, since a transition between Layer 6 and the secondary side occurs, a GND
stitching via is added to guarantee continuous ground reference of the secondary side routing of the
RESET# signal to ITP700FLEX connector.

Figure 27. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port

FO R K FO R K FO R K FO R K FO R K FO R K
855P M 855P M 855P M 855P M 855P M 855P M
MC H-M MC H-M MC H-M MC H-M MC H-M MC H-M
CPURE SET # CPURE SET # CPURE SET # CPURE SET # CPURE SET # CPURE SET #
62
L2 + L3
12.0" max
C O M M O N C O M M O N C O M M O N C O M M O N C O M M O N C O M M O N
C lock S ignals C lock S ignals C lock S ignals C lock S ignals C lock S ignals C lock S ignals
Intel Intel Intel Intel Intel Intel
855PM 855PM 855PM 855PM 855PM 855PM
M C H-M M C H-M M C H-M M C H-M M C H-M M C H-M
A D D R A D D R A D D R A D D R A D D R A D D R
L1 L1 L1 L1 L1 L1
VC C P VC C P VC C P VC C P VC C P VC C P
Rtt Rtt Rtt Rtt Rtt Rtt
Rs Rs Rs Rs Rs Rs
L2 L2 L2 L2 L2 L2
L3 Rs
0.5" max Rs = 22.6
Layer 6 Layer 6 Layer 6 Layer 6 Layer 6 Layer 6
P entium M P entium M P entium M P entium M P entium M P entium M
Intel Pentium M Intel Pentium M Intel Pentium M Intel Pentium M
processor processor processor processor
G N D G N D G N D G N D G N D G N D
VIA VIA VIA VIA VIA VIA
CPU CPU CPU CPU CPU CPU
RES ET# RES ET# RES ET# RES ET# RES ET# RES ET#
ITP FLE X ITP FLE X ITP FLE X ITP FLE X ITP FLE X ITP FLE X
CO NNECTO R CO NNECTO R CO NNECTO R CO NNECTO R CO NNECTO R CO NNECTO R
L3 L3 L3 L3 L3 L3
RES ET# RES ET# RES ET# RES ET# RES ET# RES ET#
®
Intel 855PM Chipset Platform Design Guide
Rtt
± 1% Rtt = 54.9 ± 1%
S econdary S econdary S econdary S econdary S econdary S econdary
S ide S ide S ide S ide S ide S ide
R s R s R s R s R s R s
VC C P VC C P VC C P VC C P VC C P VC C P
ITP FLEX ITP FLEX ITP FLEX ITP FLEX ITP FLEX ITP FLEX
connector connector connector connector connector connector
R
R tt R tt R tt R tt R tt R tt