Intel 855PM Design Manual page 13

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Figure 96. Hub Interface with Locally Generated Reference Voltage Divider Circuit ........... 180
Figure 97. Connection Requirements for Primary IDE Connector ........................................ 184
Figure 98. Connection Requirements for Secondary IDE Connector ................................... 185
Figure 99. PCI Bus Layout Example ..................................................................................... 188
Figure 100. Intel 82801DBM ICH4-M AC'97 - Codec Connection ....................................... 189
Figure 101. Intel 82801DBM ICH4-M AC'97 - AC_BIT_CLK Topology ............................... 190
Figure 102. Intel 82801DBM ICH4-M AC'97 - AC_SDOUT/AC_SYNC Topology ............... 190
Figure 103. Intel 82801DBM ICH4-M AC'97 - AC_SDIN Topology ..................................... 191
Figure 104. Example Speaker Circuit.................................................................................... 194
Figure 105. Recommended USB Trace Spacing .................................................................. 195
Figure 106. USBRBIAS Connection...................................................................................... 196
Figure 107. Good Downstream Power Connection............................................................... 198
Figure 108. Common Mode Choke Schematic ..................................................................... 198
Figure 109. SMBUS 2.0/SMLink Protocol ............................................................................. 201
Figure 110. High Power/Low Power Mixed V
Figure 111. FWH VPP Isolation Circuitry .............................................................................. 205
Figure 112. RTCX1 and SUSCLK Relationship in Intel 82801DBM ICH4-M........................ 206
Figure 113. External Circuitry for Intel 82801DBM ICH4-M Where the Internal RTC
is Not Used............................................................................................................. 206
Figure 114. External Circuitry for the Intel 82801DBM ICH4-M RTC.................................... 207
Figure 115. Diode Circuit to Connect RTC External Battery ................................................. 210
Figure 116. RTCRST# External Circuit for the ICH4-M RTC ................................................ 210
Figure 117. Intel 82801DBM ICH4-M/Platform LAN Connect Section.................................. 213
Figure 118. Single Solution Interconnect .............................................................................. 214
Figure 119. LAN_CLK Routing Example............................................................................... 215
Figure 120. Intel 82562ET / Intel 82562EM Termination ...................................................... 217
Figure 121. Critical Dimensions for Component Placement ................................................. 217
Figure 122. Termination Plane .............................................................................................. 219
Figure 123. Example Intel 82562ET/EM Disable and Power Down Circuitry ....................... 220
Figure 124. Trace Routing..................................................................................................... 222
Figure 125. Ground Plane Separation................................................................................... 223
Figure 126. RTC Power Well Isolation Control ..................................................................... 226
Figure 127. Intel 82801DBM ICH4-M CPU CMOS Signals with CPU and FWH .................. 227
Figure 128. Platform Clock Topology Diagram ..................................................................... 231
Figure 129. Source Shunt Termination Topology ................................................................. 232
Figure 130. Clock Skew as Measured from Agent-to-Agent................................................. 235
Figure 131. CLK66 Group Topology ..................................................................................... 236
Figure 132. AGPCLK to AGP Connector Topology .............................................................. 237
Figure 133. AGPCLK to AGP Device Down Topology.......................................................... 237
Figure 134. CLK33 Group Topology ..................................................................................... 239
Figure 135. PCICLK Group to PCI Device Down Topology .................................................. 240
Figure 136. PCICLK Group to PCI Slot Topology ................................................................. 241
Figure 137. USBCLK Group Topology .................................................................................. 242
Figure 138. CLK14 Group Topology ..................................................................................... 243
Figure 139. Platform Power Delivery Map............................................................................. 247
Figure 140. Intel
Figure 141. Example V
Figure 142. V5REF_SUS With 5V_ALWAYS Connection Option ........................................ 252
Figure 143. V5REF_SUS With 3.3V_ALWAYS and VCC5 or
VCC5_SUS Connection Option ............................................................................. 252
Figure 144. DDR Power Delivery Block Diagram.................................................................. 254
Figure 145. Decoupling Capacitors Placement and Connectivity ......................................... 264
Figure 146. Minimized Loop Inductance Example ................................................................ 266
Figure 147. Recommended Topology for Coexistence Traces............................................. 271
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Intel 855PM Chipset Platform Design Guide
855PM/82801DBM Platform Power-Up Sequence................................... 249
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/ 3.3 V Sequencing Circuitry ...................................................... 251
5REF
_ /V _ Architecture ................... 202
CC SUSPEND CC CORE
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