Intel 80219 Specification Update
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Intel 80219 Specification Update

Intel 80219 Specification Update

Intel general purpose pci processor specification update
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®
Intel
80219 General Purpose PCI
Processor
Specification Update
July 2004
®
Notice: The Intel
80219 General Purpose PCI Processor (80219) may contain design defects or
errors known as errata that may cause the product to deviate from published specifications.
Current characterized errata are documented in this specification update.
Document Number:
274020-002

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Summary of Contents for Intel 80219

  • Page 1 July 2004 ® Notice: The Intel 80219 General Purpose PCI Processor (80219) may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
  • Page 2 TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd. *Other names and brands may be claimed as the property of others.

  • Page 3: Table Of Contents

    Revision History ... 5 Preface... 6 Summary Table of Changes... 7 Identification Information...11 Core Errata ... 13 Non-Core Errata... 20 Specification Changes ... 24 Specification Clarifications ... 26 Documentation Changes ... 29 Specification Update ® Intel 80219 General Purpose PCI Processor...
  • Page 4 ® Intel 80219 General Purpose PCI Processor This Page Left Intentionally Blank Specification Update...

  • Page 5: Revision History

    Revision History Date Version July 2004 November 2003 Specification Update Intel Added Specification Clarification 7. Initial Release. ® 80219 General Purpose PCI Processor Revision History Description...

  • Page 6: Preface

    Affected Documents/Related Documents ® Intel 80219 General Purpose PCI Processor Developer’s Manual ® Intel 80219 General Purpose PCI Processor Advance Information Datasheet ® Intel 80219 General Purpose PCI Processor Design Guide Nomenclature Errata are design defects or errors. These may cause the Processor behavior to deviate from published specifications.

  • Page 7: Summary Table Of Changes

    The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the...
  • Page 8 ® Intel 80219 General Purpose PCI Processor Summary Table of Changes Core Errata Steppings Page Status NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix Boundary Scan Is Not Fully Compliant to the IEEE 1149.1 Specification Drain Is Not Flushed Correctly when Stalled in the Pipeline Undefined Data Processing-‘like’...
  • Page 9 (REQ#) The MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage (Vih) level for the PCI pins ® 80219 General Purpose PCI Processor Summary Table of Changes Errata...

  • Page 10: Specification Clarifications

    Specification Clarifications ® The Intel 80219 general purpose PCI processor is compliant with the PCI Local Bus Specification, Revision 2.2 but it is not compliant with PCI Local Bus Specification, Revision 2.3 Modifications to the Hot-Debug procedure are necessary for the Intel...

  • Page 11: Identification Information

    Identification Information Markings Figure 1. Topside Markings Specification Update ® Intel 80219 General Purpose PCI Processor FW80219Mxxx {FPO#} SLxxx © ‘2001 INTEL ® Intel 80219 General Purpose PCI Processor Identification Information...
  • Page 12 ® Intel 80219 General Purpose PCI Processor Identification Information Die Details Stepping Part Number Specification Number (SL) FW80219M400 FW80219M600 FW80219M400 FW80219M600 Device ID Registers Processor Device ID Device and Stepping (CP15, Register0 - opcode_2=0) A-0 (400 MHz) A-0 (600 MHz)

  • Page 13: Core Errata

    This would only be useful when trying to capture the data driven from the on-chip logic, during normal operation of the assembled board. However, the Intel Xscale of its clocks. Thus, even when the Intel Xscale it would be extremely difficult (or impossible) to synch the boundary scan logic with the state of the on-chip logic.

  • Page 14: Debug Unit Synchronization With The Txrxctrl Register

    ® Intel 80219 General Purpose PCI Processor Core Errata Undefined Data Processing-‘like’ Instructions are Interpreted as an MSR Instruction Problem: The instruction decode allows undefined opcodes, which look similar to the MSR (Move to Status register from an ARM register) instruction, to be interpreted as an MSR instruction. The mis-decoded MSR instruction also adds a SUBNV PC,0x4 to the instruction flow.

  • Page 15: Load Immediately Following A Dmm Flush Entry Is Also Flushed

    When the data cache unit retries an operation that is in the pending buffer, a single cycle stall occurs. Workaround: No workaround. This is a performance issue only. Status: NoFix. Specification Update ® Intel 80219 General Purpose PCI Processor Core Errata...

  • Page 16: Aborted Store That Hits The Data Cache May Mark Writeback Data As Dirty

    ® Intel 80219 General Purpose PCI Processor Core Errata Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty Problem: When there is an aborted store that hits clean data in the data cache (data in an aligned four word range, that has not been modified from the core, since it was last loaded in from memory or cleaned), the data in the array is not modified (the store is blocked), but the dirty bit is set.
  • Page 17 This precludes further memory operations from being in the pipe when the abort occurs. Load Multiple/Store Multiple that may cause precise data aborts should not be used. Status: NoFix. Specification Update ® Intel 80219 General Purpose PCI Processor Core Errata...
  • Page 18 ® Intel 80219 General Purpose PCI Processor Core Errata Accesses to the CP15 ID register with opcode2 > 0b001 returns unpredictable values Problem: The ARM Architecture Reference Manual (ARM DDI 0100E) states the following in chapter B-2, section 2.3: “If an <opcode2> value corresponding to an unimplemented or reserved ID register is encountered, the System Control processor returns the value of the main ID register.

  • Page 19: Updating The Jtag Parallel Register Requires An Extra Tck Rising Edge

    IEEE 1149.1 states that the effects of updating all parallel JTAG registers should be seen on the falling edge of TCK in the Update-DR state. The Intel Xscale incorrectly require an extra TCK rising edge to make the update visible. Therefore, operations like...

  • Page 20: Non-Core Errata

    This happens when: 1. 80219 is in PCI mode. 2. Another PCI master is attempting to access the PBI behind the 80219. 3. 16-bit mode on PBI. Workaround: The BE# signals can be used in combination with the PCE#. The BE# prevents the second CE# from being recognized by the Flash.
  • Page 21 In these situations, the MCU will drain enough data to prevent buffer overrun. Workaround: Use 64-bit memory or ECC disabled. Status: NoFix. Specification Update ® Intel 80219 General Purpose PCI Processor Non-Core Errata...
  • Page 22 (DMA, ATU, etc.). When opera- tional, the MTTR1 is intended to correct this balance. See Section 11.2.2 of the Intel General Purpose PCI Processor Developer’s Manual for more information on the MTTR1 function.
  • Page 23 Vcc specification is 3.3 V +/- 10% with the minimum Vcc specification (or minimum power level) being tested at 3.0 V. The minimum Vih level per the PCI Specification should therefore be 0.5(3.0 V) or 1.5 V. The 80219 is unable to meet this minimum Vih level at cold temperature testing specified to be 0°C.

  • Page 24: Specification Changes

    Without special control over the IDSEL signal during configuration cycles, the host and the 80219 may both attempt to configure the same I/O device. By taking control of IDSEL, the 80219 can execute configuration cycles to the slave I/O device (SCSI) and properly hide the slave I/O device from the host and operating system initiated configuration cycles.
  • Page 25 Note: The host BIOS does not require any modifications to accommodate this implementation. All the responsibility for I/O device configuration and resource falls to the 80219 firmware. ® Figure 2. Intel 80219 General Purpose PCI Processor P_BMI Signal Implementation for ®...

  • Page 26: Specification Clarifications

    Addendum to the PCI Local Bus Specification, Revision 1.0a, that calls out compliance with the PCI Local Bus Specification, Revision 2.2. Since the release of the 80219, the PCI Special Interest Group has released a new specification revision, PCI Local Bus Specification, Revision 2.3.
  • Page 27 Writes Issue: In 80219-based applications that run the PCI bus segment in 32-bit PCI Mode or 64-bit PCI Mode with 32-bit targets, write transactions that are on unaligned 64-bit addresses are promoted to 64-bit aligned writes. The first half of the 64-bit write is on a 64-bit aligned address and has the BE# signals disabled.
  • Page 28 80219 General Purpose PCI Processor contains several reserved registers. The Intel ® 80219 General Purpose PCI Processor Developer’s Manual (Section 15.5 Table 273) states that memory map register locations FFFFE800H - FFFFE8FFH are reserved. Writing to these can cause the processor to enter an undesired state.

  • Page 29: Documentation Changes

    ® Intel 80219 General Purpose PCI Processor Documentation Changes Documentation Changes None for this revision of this specification update. Specification Update...
  • Page 30 ® Intel 80219 General Purpose PCI Processor Documentation Changes This Page Left Intentionally Blank Specification Update...

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