Itp Interposer - Intel 855PM Design Manual

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14.4.2.2.

ITP Interposer

Pin Name System
Pull up/Pull down
BPM[5:0]#
DBA# Pull up to target
VCC
DBR# Pull up to
V3ALWAYS
RESET#
TCK Pull down to GND
TDI Pull up to VCCP
TDO
TMS Pull up to VCCP
TRST# Pull down to GND
NOTES:
1. See Section 14.4.2.1 if ITP700FLEX connector is implemented.
2. See Section 14.4.2.3 if NO processor ITP debug port solution is implemented.
3. Default tolerance for resistors is +/-5% unless otherwise specified.
®
Intel 855PM Chipset Platform Design Guide
1, 2
ITP Interposer
Series Termination
Resistor (
150 - 240
150 - 240
27
150
39
680
Platform Design Checklist
Notes
Leave the signals as NC (No Connect).
DBA# is an optional signal that may be
implemented when an ITP Interposer is
used.
ITP Interposer supported Validation
Systems:
Pull up resistor should be placed within
1 ns of CPU socket.
ITP Interposer supported Production
Systems:
Leave this signal as NC (No Connect).
See section 4.3.2 and 4.3.2.2 for more
details.
ITP Interposer supported Validation
Systems
This signal needs to be routed to
system reset logic (e.g. SYS_RESET#
of ICH4-M). Pull up resistor must be
placed within 1ns of CPU socket.
ITP Interposer supported Production
Systems:
Pull up may be required depending on
impact to system reset logic that it is
connected to.
See section 4.3.2 and 4.3.2.2 for more
details.
See RESET# in Section 14.4.1.
Pull down needs to be placed within
2.0" of CPU socket.
Pull up needs to be placed within 2.0" of
CPU socket.
Leave this signal as NC (No Connect)
Pull up needs to be placed within 2.0" of
CPU socket.
Pull down needs to be placed within
2.0" of CPU socket.
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