Table of Contents
Advertisement
R
Figure 161. LAN_RST# Design Recommendation (On Intel CRB)
14.11.1.2. Decoupling Recommendations
Signal Name
VccLan3_3
VccLan_L3_3
LAN_X1, LAN_X2
NOTE: All decoupling guidelines are recommendations based on our reference board design. Customers will need to take their layout,
and PCB board design into consideration when deciding on their overall decoupling solution.
®
Intel
855PM Chipset Platform Design Guide
VccS us3_3LAN
LA N_R S T
LAN – Decoupling Recommendations
Configuration
F
Pull down to GND
0.1 µF
4.7 µF
Pull down to GND
0.1 µF
4.7 µF
Pull down to GND
22 pF
82562E M
10k
IS O L_TC K
IS O L_TI
IS O L_E X
1
Qty
4
2
1
1
1
Each pin requires a decoupling cap
Platform Design Checklist
Notes
327
Advertisement
Table of Contents
