Page 1 Intel 852PM Chipset Platforms Design Guide ® ® For Use with the Mobile Intel Pentium 4 Processor supporting Hyper- ® Threading Technology on 90-nm process technology, Mobile Intel ® ® ® ® ® Pentium 4 Processor, Intel Celeron Processor, and Intel...
Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Page 3: Table Of Contents
Mobile Intel Pentium 4 Processor supporting Hyper-Threading Technology on 90-nm process technology ........23 2.1.1.2. Mobile Intel Pentium 4 Processor ...........24 2.1.1.3. Intel Celeron D Processor on 90 nm process and in the 478-pin package...................25 2.1.1.4. Intel Celeron Processor ..............25 2.1.2.
Page 4 4.5.1.1. Mechanical Considerations ............57 4.5.1.2. Electrical Considerations ..............57 4.6. Mobile Intel Pentium 4 Processor and 852GME/852GMV/852PMChipset FSB Signal Package Lengths ......................58 Platform Power Requirements ....................63 System Memory Design Guidelines (DDR-SDRAM) ..............65 6.1. Length Matching and Length Formulas................. 66 6.2.
Page 5 RAMDAC/Display Interface................109 7.1.2. Reference Resistor (REFSET)..............109 7.1.3. RAMDAC Board Design Guidelines.............110 7.1.4. RAMDAC Routing Guidelines ..............111 7.1.5. DAC Power Requirements ................113 7.1.6. HSYNC and VSYNC Design Considerations..........114 ® ® ® Intel 852GME, Intel 852PM and Intel 852GMV Chipset Platforms Design Guide...
Page 6 Hub Interface..........................140 9.1. Hub Interface Compensation ..................140 9.2. Hub Interface Data HL[10:0] and Strobe Signals............141 9.2.1. HL[10:0] and Strobe Signals Internal Layer Routing ........141 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 7 10.6.1.2. General Design Issues/Notes ............167 10.6.1.3. High Power/Low Power Mixed Architecture........167 10.6.1.4. Calculating the Physical Segment Pull-Up Resistor .....167 10.7. FWH ..........................169 10.7.1. FWH Decoupling ..................169 ® ® ® Intel 852GME, Intel 852PM and Intel 852GMV Chipset Platforms Design Guide...
Page 8 10.9.3.5.2. Termination Plane Capacitance ......... 183 10.9.4. Intel 82562ET/EM Disable Guidelines............184 10.9.5. Design and Layout Consideration for Intel 82540EP / 82551QM ....184 10.9.6. General Intel 82562ET/82562EM/82551QM/82540EP Differential Pair Trace Routing Considerations ..............185 10.9.6.1.1. Trace Geometry and Length ........186 10.9.6.1.2.
Page 9 Platform Power Requirements..................208 12.3. Voltage Supply......................209 12.3.1. Power Management States................209 12.3.2. Power Supply Rail Descriptions..............210 12.4. 852GME/852GMV/852PMGMCH/ICH4-M Platform Power-Up Sequence ....211 12.4.1. ICH4-M Power Sequencing Requirements..........213 12.4.1.1. 3.3 V/1.5 V Power Sequencing .............213 12.4.1.2. / 3.3 V Sequencing..............213 5REF 12.4.1.3.
Page 10 12.11. Thermal Design Power....................233 Test Signals ..........................234 13.1. Mobile Intel Pentium 4 Processor Reserved Signals ..........234 13.2. Intel 852GME / 852PM GMCH RSVD Signals ............235 Platform Design Checklist......................236 14.1. General Information..................... 236 14.2. Customer Implementation of Voltage Rails..............237 14.3.
Page 11 14.11. FWH Checklist ......................275 14.11.1. Resistor Recommendations.................275 14.12. LAN/HomePNA Checklist ....................275 14.12.1. Resistor Recommendations (for 82562ET / 82562 EM) ......275 14.12.2. Decoupling Recommendations ..............276 Schematics ..........................277 ® ® ® Intel 852GME, Intel 852PM and Intel 852GMV Chipset Platforms Design Guide...
Page 12 Figures Figure 1. Intel 852GME GMCH System Block Diagram ............29 Figure 2. Intel 852PM Chipset System Block Diagram............32 Figure 3. Intel 852GMV GMCH System Block Diagram ............36 Figure 4. Recommended Board Stack-Up Dimensions............38 Figure 5. Cross-Sectional View of 2:1 Ratio ................42 Figure 6.
Page 13 Figure 56. Connection Requirements for Secondary IDE Connector ........150 Figure 57. PCI Bus Layout Example ..................153 Figure 58. Intel 82801DBM ICH4-M AC’97 – Codec Connection ......... 154 Figure 59. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology ......... 155 Figure 60.
Page 14 Figure 112. Clock Power-down Implementation ..............246 Figure 113. Reference Voltage Level for SMVREF ............... 248 Figure 114. 852GME HXSWING & HYSWING Reference Voltage Generation Circuit ..250 Figure 115. DPMS Clock Implementation................253 Figure 116. Q-SWITCH Circuit ....................254 Figure 117.
Page 15 Table 12. Layout Recommendation for COMP[1:0] ..............55 Table 13. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector..57 Table 14. Mobile Intel Pentium 4 Processor and 852GME Chipset Package Lengths... 58 Table 15. GMCH/MCH Chipset Memory Signal Groups ............65 Table 16.
Page 16 Table 88. Absolute vs. Relative Voltage Specification............219 Table 89. DDR-SDRAM SO-DIMM Voltage and Current Requirements....... 219 Table 90. Intel GMCH System Memory Voltage and Current Requirements ......220 Table 91. Termination Voltage and Current Requirements ........... 220 Table 92. GMCH System Memory I/O SMVREF Calculation ..........221 Table 93.
Page 17 Table 100. Icc Maximum Sustained Estimates (Icc REV0.3)..........232 Table 101. Intel ICH4-M Power Consumption Measurements..........232 Table 102. Intel 852GME/852GMV/852PMGMCH Component Thermal Design Power ..233 Table 103. Intel ICH4-M Component Thermal Design Power..........233 Table 104. GMCH “Intel Reserved” Signal Pin-Map Locations..........235 Table 105.
Page 18 Added information for Mobile Intel Pentium 4 Processor supporting Hyper-Threading Technology on 90-nm process technology -004 253026 Updates include: June 2004 Added information for Intel Celeron D Processor on 90 nm process and in the 478-pin package ® ® ® Intel...
Page 19: Introduction
Intel Celeron D processor on 90 nm process and in the 478-pin package in combination with the 852GME, 852GMV or 852PM deliver high performance and professional mobile platform solution using internal and/or external graphics. Section 2 provides an overview of system features of supported processor and chipset combinations.
Page 20: Referenced Documents
Intel Celeron D Processor on 90 nm Process and in the 478-pin Package Datasheet ® ® http://developer.intel.com/ Intel 852GME Chipset GMCH and Intel 852PM Chipset MCH Datasheet ® ® http://developer.intel.com/ Intel 852GME and Intel 852PM Chipset GMCH Specification Update ®...
Page 21: Conventions And Terminology
Serial Presence Detect S/PDIF Sony*/Phillips* Digital Interface Suspend-To-Disk Suspend-To-Ram Total Cost of Ownership UBGA Micro Ball Grid Array Universal Serial Bus Voltage Regulator Module ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 22 Introduction This page intentionally left blank. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 23: System Overview
82801DBM I/O Controller Hub (ICH4-M) Datasheet. 2.1.1. Host Interface The Intel 852GME GMCH can utilize a single processor. It supports a FSB frequency of 400/533 MHz (100/133 MHz HCLK respectively) using scaleable FSB VCC. 2.1.1.1. Mobile Intel Pentium 4 Processor supporting Hyper-Threading Technology on 90-nm process technology Intel’s Mobile Intel®...
Page 24: Mobile Intel Pentium 4 Processor
System Overview its predecessor, the Mobile Intel Pentium 4 processor in the 478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software. The Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology supports Hyper-Threading Technology.
Page 25: Intel Celeron D Processor On 90 Nm Process And In The 478-Pin Package
DVO Interface 2.1.2.1. The 852GME GMCH multiplexes an AGP interface with two Intel DVOs. The DVO ports can each support a single channel DVO device. If both ports are active in single channel mode, they will have identical display timings and data. Alternatively the DVO ports can combine to support dual channel devices supporting higher resolutions and refresh rates.
Page 26: Accelerated Graphics Port (Agp) Interface
Dual independent pipe for dual independent display Simultaneous display: same images and native display timings on each display device Digital Video Out Port (DVOB & DVOC) support ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 27: Package/Power
VCCSM, VCCQSM, VCCTXLVDS (2.5 V) VCCGPIO (3.3 V) 2.1.4. Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) Upstream Accelerated Hub Architecture interface for access to the GMCH PCI 2.2 interface (6 PCI Request/Grant Pairs) Bus Master IDE controller (supports Ultra ATA 100/66/33) USB 1.1 and USB 2.0 Host Controllers...
Page 28: Firmware Hub (Fwh)
Firmware Hub (FWH) An integrated hardware Random Number Generator (RNG) Register-based locking Hardware-based locking 5 GPIs Package/Power 32-pin TSOP/PLCC 3.3-V core and 3.3 V/12 V for fast programming ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 29: Figure 1. Intel 852Gme Gmch System Block Diagram
System Overview Figure 1. Intel 852GME GMCH System Block Diagram Intel Processor 400/533 MHz PSB LVDS Panel Intel® 852GME 200/266/333MHz GMCH DVO Device / 732 Micro-FCBGA DVO/AGP Graphic Controller 266 MHz HUB Interface ATA100 IDE (2) Intel ® 82801 DBM ICH4-M USB 2.0/1.1 (6)
Page 30: Intel 852Pm Chipset Platform System Features
System Overview 2.2. Intel 852PM Chipset Platform System Features The 852PM chipset contains two core components: the Intel 852PM GMCH and the Intel ICH4-M. The MCH integrates following: 533 MHz FSB controller 266/333 MHz DDR controller DVO muxed AGP interface...
Page 31: Integrated System Memory Dram Controller
VCC, VCCASM, VCCHL, VCCAHPLL, VCCAGPLL, VCCADPLLA, VCCADPLLB (1.5 V) VCCADAC, VCCDVO, VCCDLVDS, VCCALVDS, (1.5 V) VCCSM, VCCQSM, VCCTXLVDS (2.5 V) VCCGPIO (3.3 V) 2.2.4. Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) Please refer to Section 2.1.4. 2.2.5. Firmware Hub (FWH) Please refer to Section 2.1.5.
Page 32: Figure 2. Intel 852Pm Chipset System Block Diagram
System Overview Figure 2. Intel 852PM Chipset System Block Diagram Intel® Processor 400/533MHz Intel 200/266/333 852PM AGP 2.0 Controller 732 Micro-FCBGA Interface ATA100 IDE (2) Intel 82801 DBM 421 BGA (ICH4-M) 421 BGA USB 2.0/1.1 (6) PCI 33MHz AC’97 2.2...
Page 33: Intel 852Gmv Chipset Platform System Features
AC’97 digital controller and a hub interface for communication with the GMCH. The 852GME GMCH is a Graphics Memory Controller Hub (GMCH) designed for Mobile Intel Pentium 4 processor, Intel Celeron processor and Intel Celeron D processor on 90 nm process and in the 478- pin package..
Page 34: Integrated System Memory Dram Controller
Compliant with ANSI/TIA/EIA –644-1995 spec Integrated PWM interface for LCD backlight inverter control Bi-linear Panel fitting 2.3.3. Package/Power 732-pin Micro-FCBGA (37.5 mm x 37.5 mm) VTTLF, VTTHF (1.05 V) ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 35: Intel 82801Dbm I/O Controller Hub 4-Mobile (Ich4-M)
VCCSM, VCCQSM, VCCTXLVDS (2.5 V) VCCGPIO (3.3 V) 2.3.4. Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) Upstream Accelerated Hub Architecture interface for access to the GMCH PCI 2.2 interface (6 PCI Request/Grant Pairs) Bus Master IDE controller (supports Ultra ATA 100/66/33) USB 1.1 and USB 2.0 Host Controllers...
Page 36: Figure 3. Intel 852Gmv Gmch System Block Diagram
System Overview Figure 3. Intel 852GMV GMCH System Block Diagram ® ® Intel Celeron Processor or ® ® Intel Celeron Processor 400/533 MHz LVDS Panel Intel® 852GMV 200/266MHz GMCH DVO Device 732 Micro-FCBGA Graphic Controller 266 MHz HUB Interface ATA100 IDE (2) Intel ®...
Page 37: General Design Considerations
Note: If the guidelines listed in this document are not followed, then thorough signal integrity and timing simulations should be completed for each design. Even when the guidelines are followed, Intel recommends that critical signals be simulated to ensure proper signal integrity and flight time. Any deviation from the guidelines should be simulated.
Page 38: Figure 4. Recommended Board Stack-Up Dimensions
(4.5-mil prepeg thickness) L7 ground plane. The benefit of such a stack-up is low inductance power delivery. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 39: Alternate Stack Ups
Note: If Intel’s recommended stackup guidelines are not used, then the OEM is liable for all aspects of their board design (for example, understanding impacts of SI and power distribution, etc.) ®...
Page 40 General Design Considerations This page intentionally left blank. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 41: Fsb Design Guidelines
FSB Design Guidelines FSB Design Guidelines The following layout guidelines support designs using the Mobile Intel Pentium 4 processor and the ® Intel 852GME/852GMV/852PMchipset. Due to on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be placed on the motherboard for most FSB signals.
Page 42: Figure 5. Cross-Sectional View Of 2:1 Ratio
Refer to Intel ® ® 852PM Chipset MCH Datasheet for GMCH package 852GME Chipset GMCH and Intel dimensions and refer to the Mobile Intel ® ® ® ® Pentium 4 Processor Datasheet or Mobile Intel...
Page 43: Return Path Evaluation
60 . In order for the platform to be compatible with the Mobile Intel Pentium 4 processor, this pin should be left as NC. If a platform is only used with the Mobile Intel Pentium 4 processor, then this pin can be connected to GND.
Page 44: General Topology And Layout Guidelines
(cs_pkglen cs_pkglen net,strobe strobe strobe Refer to the Intel ® 852GME Chipset GMCH and Intel® 852PM Chipset MCH Datasheet for GMCH package dimensions and refer to the Mobile Intel ® ® 4 Processor Datasheet and the Mobile Pentium ® ®...
Page 45: Source Synchronous (Ss) Signals
The complement strobe must be routed to within ± 0.025 inches of the associate “reference” strobe. All traces within each signal group must be routed on the same layer (required). Intel recommends that length of the strobes be centered to the average length of associated data or address traces to maximize setup/hold time margins.
Page 46: Common Clock (Cc) Agtl+ Signals
For these signals Rtt should be placed near CPU: L2<= 0.5 inches. Rtt = 51.1 ±1%. Routing these signals to 4.0 inches ± 0.5 inches should maximize the setup and hold margin parameters while adhering to expected mobile solution design constraints. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 47: Asynchronous Agtl+ Signals
Due to the dependencies on system design implementation, IERR# can be implemented in a number of ways to meet design goals. IERR# can be routed as a test point or to any optional system receiver. Intel recommends that the FERR# signal of the Mobile Intel Pentium 4 processor be routed to the FERR# signal of the Intel ICH4-M.
Page 48: Topology 1B: Open Drain (Od) Signals Driven By The Processor -Thermtrip
THERMTRIP# can be implemented in a number of ways to meet design goals. It can be routed to the ICH4-M or any optional system receiver. Intel recommends that the THERMTRIP# signal of the processor be routed to the THRMTRIP# signal of the ICH4-M. The ICH4-M’s THRMTRIP# signal is a new signal to the I/O controller hub architecture that allows the ICH4-M to quickly put the whole system into an S5 state whenever the catastrophic thermal trip point has been reached.
Page 49: Topology 1C: Open Drain (Od) Signals Driven By The Processor -Prochot
T-split from the PROCHOT# signal. The pull-up voltage for termination resistor Rtt is VCCP. Intel recommends that PROCHOT# be routed using the voltage translation logic shown in Figure 11. Figure 11. Routing Illustration for Topology 1C...
Page 50: Topology 2A: Open Drain (Od) Signals Driven By Ich4-M - Pwrgood
± 15% characteristic trace impedance. The pull-up voltage for termination resistor Rtt is VCC_CORE. Note: The Intel ICH4-M’s CPUPWRGD signal should be routed point-to-point to the Mobile Intel Pentium 4 processor’s PWRGOOD signal. The routing from the Mobile Intel Pentium 4 processor’s PWRGOOD pin should fork out to both the termination resistor, Rtt, and the ICH4-M.
Page 51: Topology 2B: Cmos Signals Driven By Ich4-M - Dpslp
The routing of DPSLP# at the CPU should fork out to both the ICH4-M and the GMCH. Segments L1 and L2 from Table 9 should not T-split from a trace from the Mobile Intel Pentium 4 processor pin.
Page 52: Topology 2C: Cmos Signals Driven By Ich4-M - A20M#, Ignne#, Lint0/Intr, Lint1/Nmi, Slp#, Smi#, And Stpclk
The Topology 2C CMOS A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK# signals should implement a point-to-point connection between the ICH4-M and the Mobile Intel Pentium 4 processor. The routing guidelines allow both signals to be routed as either micro-strip or strip-lines using 53 ±...
Page 53: Topology 3: Cmos Signals Driven By Ich4-M To Cpu And Fwh - Init
± 5% 1.3 k ± 5% ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” ± 5% 1.3 k ± 5% ± 5% Strip-line ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 54: Voltage Translation Circuit
4.3.8. AGTL+ I/O Buffer Compensation The Mobile Intel Pentium 4 processor has two pins, COMP[1:0], and the 852GME / 852PM chipset GMCH has two pins, HXRCOMP and HYRCOMP, that require compensation resistors to adjust the AGTL+ I/O buffer characteristics to specific board and operating environment characteristics. Also, the GMCH requires two special reference voltage generation circuits to pins HXSWING and HYSWING for the same purpose described above.
Page 55: Mobile Intel Pentium 4 Processor Agtl+ I/O Buffer Compensation
FSB Design Guidelines 4.3.8.1. Mobile Intel Pentium 4 Processor AGTL+ I/O Buffer Compensation The COMP[1:0] signals adhere to the following routing recommendation. Table 12 illustrates the recommendation topology. Table 12. Layout Recommendation for COMP[1:0] Trace width Trace Spacing 15 mil 25 mils 0.5 inches Maximum...
Page 56: Figure 18. Processor Reset# Signal Routing Topology With No Itp700Flex Connector
Figure 19. Processor RESET# Signal Routing Topology with ITP700FLEX Connector VVC_CORE GMCH RESET# CPURESET# ITPFLEX Connector RESET# ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 57: Host Vrefs
The LAI is installed between the processor socket and the Mobile Intel Pentium 4 processor. The LAI pins plug into the socket, while the Mobile Intel Pentium 4 processor plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the Mobile Intel Pentium 4 processor and a logic analyzer.
Page 58: Mobile Intel Pentium 4 Processor And 852Gme/852Gmv/852Pmchipset Fsb Signal Package Lengths
Refer to Section 4.1 for further details. The Mobile Intel Pentium 4 processor and 852GME GMCH package traces are routed as micro-strip lines with a nominal characteristic impedance of 53 ±...
Page 59 0.515 HD[8]# D[9]# 0.590 HD[9]# D[10]# 0.274 HD[10]# D[11]# 0.203 HD[11]# D[12]# 0.589 HD[12]# D[13]# 0.462 HD[13]# D[14]# 0.183 HD[14]# D[15]# 0.550 HD[15]# DBI[0]# 0.309 DINV[0]# ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 60 0.371 HD[35]# D[36]# 0.271 HD[36]# D[37]# 0.454 HD[37]# D[38]# 0.437 HD[38]# D[39]# 0.383 HD[39]# D[40]# 0.165 HD[40]# D[41]# 0.343 HD[41]# D[42]# 0.381 HD[42]# D[43]# 0.329 HD[43]# ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 61 0.426 HD[57]# D[58]# 0.336 HD[58]# D[59]# 0.386 HD[59]# D[60]# 0.222 HD[60]# D[61]# AA25 0.426 HD[61]# D[62]# AA22 0.268 HD[62]# D[63]# AA24 0.394 HD[63]# DBI[3]# 0.202 DINV[3]# ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 62 FSB Design Guidelines This page intentionally left blank. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 63: Platform Power Requirements
Platform Power Requirements Platform Power Requirements Please contact your Intel field representative for more information on the electrical requirements for the DC-to-DC voltage regulator for the Mobile Intel Pentium 4 processor and Intel Celeron processor. ® ® ® Intel 852GME, Intel...
Page 64 Platform Power Requirements This page intentionally left blank. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 65: System Memory Design Guidelines (Ddr-Sdram)
System Memory Design Guidelines (DDR-SDRAM) The Intel 852GME/852GMV/852PMGMCH/MCH Double Data Rate (DDR) SDRAM system memory interface consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several signal groups: Data, Control, Command, CPC, Clock, and Feedback signals. Table 15 summarizes the different signal groupings.
Page 66: Length Matching And Length Formulas
A simple summary of the length matching formulas for each signal group is provided in the tables below. Table 16. Intel 852GME/852GMV/852PMChipset GMCH/MCH DDR 333 Length Matching Formulas Signal Group Minimum Length...
Page 67: Topologies And Routing Guidelines
S O - D I M M P A D S G M C H P i n D i f f e r e n t i a l P a i r s ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 68: Memory Clock Routing Guidelines
2. The DDR clocks should be routed on internal layers, except for pin escapes. It is recommended that pin escape vias be located directly adjacent to the ball pads on all clocks. Surface layer routing should be minimized. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 69: Clock Length Matching Requirements
X1, in Figure 21. These are the lengths to which all clocks within the corresponding group will be matched and the reference length values used to calculate the length ranges for the other signal groups. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 70: Clock Reference Lengths
N o te : A ll le n g th s a re m e a s u re d fro m G M C H d ie -p a d to S O -D IM M 1 c o n n e c to r p a d s . ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 71: Clock Package Length Table
SCK/SCK# exactly, or alternatively the average package length can be used for both outputs of a pair and length tuning done with respect to the motherboard portion only. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 72: Clock Routing Example
After the series resistor, the signal should transition from the external layer to the same internal layer and route to SO-DIMM0. At SO-DIMM0, ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 73 The table and diagrams below depict the recommended topology and layout routing guidelines for the DDR-SDRAM data signals. Intel recommends that the full data bus SDQ[71:0], mask bus SDM[8:0], and strobe signals SDQS[8:0] be routed on the same internal signal layer. It is required that the SDQ byte group and the associated SDM and SDQS signals within a byte lane be routed on the same internal layer.
Page 74: Data Bus Topology
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR related signals. Data signals should be routed on inner layers with minimized external trace lengths. Table 20. Intel 852GME Chipset GMCH/MCH Memory Data Signal Group Routing Guidelines Parameter...
Page 75: Sdqs To Clock Length Matching Requirements
Length matching is only performed from the GMCH/MCH to the SO-DIMMs, and does not involve the length of L4, which can vary over its entire range. Intel recommends that routing segment length L3 between SO-DIMM0 to SO-DIMM1 be held fairly constant and equal to the offset between clock reference lengths X0 and X1.
Page 76: Figure 24. Sdqs To Clock Trace Length Matching Diagram
N o te : A ll le n g ths a re m e asu re d fro m G M C H d ie - p a d to S O -D IM M c o n n e cto r p a d . ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 77: Data To Strobe Length Matching Requirements
SDM[0] SDQS[0] SDQ[15:8] SDM[1] SDQS[1] SDQ[23:16] SDM[2] SDQS[2] SDQ[31:24] SDM[3] SDQS[3] SDQ[39:32] SDM[4] SDQS[4] SDQ[56:40] SDM[5] SDQS[5] SDQ[55:48] SDM[6] SDQS[6] SDQ[63:56] SDM[7] SDQS[7] SDQ[71:64] SDM[8] SDQS[8] ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 78: Figure 25. Sdq/Sdm To Sdqs Trace Length Matching Diagram
SDQ[6] (X +/-25 mils) SDQ[7] SDM[0] SDM Length (Y) = (X ±25 mils) Note: All lengths are measured from GMCH die- pad to SO-DIMM connector pads. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 79: Sdq/Sdqs Signal Package Lengths
SDQ_22 AF10 SDQ_46 AH21 SDQ_70 AF16 SDQ_23 AE11 SDQ_47 AG22 SDQ_71 AF17 SDM_0 SDQS_0 SDM_1 SDQS_1 SDM_2 SDQS_2 SDM_3 AH12 SDQS_3 AE12 SDM_4 AD19 SDQS_4 AH17 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 80: Memory Data Routing Example
R-pack placement. Figure 26. Data Signals Group Routing Example From GMCH/MCH Data Signals ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 81: Control Signals - Scke[3:0], Scs#[3:0]
All internal and external signals should be ground reference to keep the path of return current continuous. Intel suggests that all control signals be routed on the same internal layer.
Page 82: Control Signal Topology
Length Matching Requirements Section 6.3.3.3 and Figure 28. NOTES: 1. Recommended resistor values and trace lengths may change in a later revision of the design guide. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 83: Control To Clock Length Matching Requirements
CS/CKE package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 84: Figure 28. Control Signal To Clock Trace Length Matching Diagram
SCKE[3:2] CNTRL Length = Y1 GMCH SCK[5:3] Clock Ref. Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pads. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 85: Memory Control Routing Example
Memory Control Routing Example Figure 29 is an example of a board routing for the Control signal group. Figure 29. Control Signals Group Routing Example From GMCH Control Signals ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 86: Control Group Package Length Table
SO-DIMM, when there is no room between the two connectors. Note that series resistors are essential in all of the three topologies. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 87: Command Topology 1
Rt. Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous.
Page 88: Command Topology 1 Routing Guidelines
3. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching requirements. 4. It is possible to route using four vias if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 89: Command Topology 1 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 90: Figure 31. Topology 1 Command Signal To Clock Trace Length Matching Diagram
RAS#, CAS#, CMD Length = Y1 GMCH SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 91: Command Topology 2
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non- DDR related signals. Command signals should be routed on inner layers with minimized external trace lengths. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 92: Command Topology 2 Routing Guidelines
L1 to series termination and if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 93: Command Topology 2 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 94: Figure 33. Topology 2 Command Signal To Clock Trace Length Matching Diagram
GMCH Package CMD Length = Y1 GMCH SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 95: Command Topology 2 Routing Example
Command Topology 2 Routing Example Figure 34 is an example of a board routing for the Command signal group. Figure 34. Example of Command Signal Group From GMCH Command Signals ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 96: Command Topology 3
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous.
Page 97: Command Topology 3 Routing Guidelines
L1 to series termination and if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 98: 6.3.4.10. Command Topology 3 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 99: Figure 36. Topology 3 Command Signal To Clock Trace Length Matching Diagram
RAS#, CAS#, CMD Length = Y1 GMCH SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 100: 6.3.4.11. Command Group Package Length Table
Signal Pin Number (mils) SMA[0] AC18 SMA[3] AD17 SMA[6] SMA[7] SMA[8] SMA[9] SMA[10] AC19 SMA[11] SMA[12] SBA[0] AD22 SBA[1] AD20 SCAS# AC24 SRAS# AC21 SWE# AD25 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 101: Cpc Signals - Sma[5,4,2,1], Smab[5,4,2,1]
All internal and external signals should be ground reference to keep the path of return current continuous. Intel suggests that all CPC signals be routed on the same internal layer.
Page 102: Cpc Signal Topology
Trace Length L2 – SO-DIMM Via to Parallel Termination Resistor Max = 2.0 inches Parallel Termination Resistor (Rt) ± 5% Maximum Recommended Motherboard Via Count Per Signal ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 103: Cpc To Clock Length Matching Requirements
CPC package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 104: Cpc Group Package Length Table
Pkg Length Pkg Length Signal Signal Number (mils) Number (mils) SMA[1] AD14 SMAB[1] AD16 SMA[2] AD13 SMAB[2] AC12 SMA[4] AD11 SMAB[4] AF11 SMA[5] AC13 SMAB[5] AD10 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 105: Feedback - Rcvenout#, Rcvenin
Routing Updates for “High-Density” Memory Device Support Simulation results show that the current DDR layout and routing guidelines for the Intel 852GME/852GMV/852PMchipset-based platforms can support “high-density” SO-DIMM memory modules. Please contact your Intel field representative for command signal group related BIOS settings for supporting high-density SO-DIMM modules.
Page 106: Ddr Memory Ecc Functionality Disable
On platforms where ECC memory is supported, it is important that all relevant SDQ, SDQS, and SCK signals to the SO-DIMMs be disabled when the system is populated with only non-ECC or a combination of ECC and non-ECC memory. Please contact your Intel field representative for information on memory initialization and register programming. 6.5.2.
Page 107: External Thermal Sensor Based Throttling (Ets#)
Ideally, one thermal sensor should be placed near each SO-DIMM in a system. The thermal sensor should be located in an area ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 108: Figure 39. Ddr Memory Thermal Sensor Placement
15 mm (0.6 inches) of the outline/SO-DIMM shadow. Again, this assumes negligible effects from airflow. Please refer to the Intel ® 852GM Chipset Mobile Thermal Design Guide for more details.
Page 109: Integrated Graphics Display Port
Integrated Graphics Display Port Integrated Graphics Display Port Note: This section of this document applies to Intel 852GME GMCH chipsets. The GMCH contains four display ports: an analog CRT port, a dedicated LVDS port, and two 12-bit Digital Video Out (DVO) ports. Section 7.1 will discuss the CRT and RAMDAC routing requirements.
Page 110: Ramdac Board Design Guidelines
R, G, B signal be routed single-endedly. The analog RGB signals should be routed with an impedance of 37.5 . Intel recommends that these be routed on an inner routing layer and that it be shielded with VSS planes, if possible. Spacing between DAC channels and to other signals should be maximized;...
Page 111: Ramdac Routing Guidelines
Place ESD diodes to Do NOT route any high- minimize power rail frequency signals in the inductance – place C1 as shaded area close to diodes as possible ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 112: Table 33. Recommended Gmch Dac Components
Rated for a continuous Ron < 8 , Con < 10pF Switch channel current of 100 Texas Instruments SN74CB3Q3306 mA (min) Not needed when using 852PM platform or 852GME platform with external graphics. NOTE: ® ® ® Intel 852GME, Intel...
Page 113: Dac Power Requirements
Designs should provide as clean and quiet a supply as possible to the VCCA_DAC. Additional filtering and/or separate voltage rail may be needed to do so. On the Intel CRB, there is a placeholder for a LC filter in case there is noise present in the VCCA power rail.
Page 114: Hsync And Vsync Design Considerations
3.3-V outputs from the GMCH. Some monitors have been found to drive HSYNC and VSYNC signals during reset. Because these signals are used as straps on the 852GME, the GMCH can enter an illegal state under these conditions. In order to prevent these signals from being driven to the GMCH during reset, system designers must ensure the GMCH is isolated from any monitor driving HSYNC or VSYNC while PCI_RST# is active.
Page 115: Lvds Length Matching Constraints
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as secondary operation.
Page 116: Lvds Routing Guidelines
Breakout Exceptions maintain trace width as 4 mils, spacing 7 mils, while the spacing (Reduced geometries for GMCH breakout region) between pairs can be 10-20 mils. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 117: Table 36. Lvds Package Lengths
IYAP1 487.5 IYBP1 524.7 CHANNEL CHANNEL IYAM1 466.2 IYBM1 516.6 IYAP2 572.6 IYBP2 623.3 IYAM2 566.2 IYBM2 604.2 IYAP3 643.2 IYBP3 441.8 IYAM3 637.8 IYBM3 441.7 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 118: Digital Video Out Port
7.3. Digital Video Out Port The 852GME GMCH digital video out (DVO) port interface supports a wide variety of third party DVO compliant devices (e.g. TV encoder, TMDS transmitter or integrated TV encoder and TMDS transmitter).The 852GME has two dedicated DVO’s (DVOB and DVOC). Intel’s DVO port is a 1.5-V only interface that can support transactions up to 165 MHz.
Page 119: Common Signals For Both Dvo Ports
DVORCOMP GVREF 7.3.2. DVOB and DVOC port Interface Routing Guidelines For 852GME platforms, guidelines will apply for both interfaces. 7.3.2.1. Length Mismatch Requirements The routing guidelines presented in the following subsections define the recommended routing topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for each signal group, which are recommended to achieve optimal SI and timing.
Page 120: Package Length Compensation
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as secondary operation.
Page 121: Table 39. Dvob Interface Package Lengths
In order to break out of the 852GME GMCH, the DVOB and/or DVOC data signals can be routed with a trace width of 4 mils and a trace spacing of 7 mils. The signals should be separated to a trace width of 4 mils and a trace spacing of 8 mils within 0.3 inches of the GMCH component.
Page 122: Dvob And Dvoc Port Termination
ISI induced skews. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 123: Dvob And Dvoc Simulation Method
SSO (ISI, ground bounce, etc.) should be accounted for in the timing budget as they will reduce the total available margin for the design. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 124: Dvob And Dvoc Port Flexible (Modular) Design
Data Setup to Strobe tDSu Data Hold from Strobe All numbers in this table are from the 852GME GMCH specification documents that are applicable for this NOTE: interface. For third party receiver devices, please refer to appropriate third party vendor specifications.
Page 125: Generic Connector Model
Pull-ups (or pull-ups with the appropriate value derived from simulating the signal) typically ranging from 2.2 k to 10 k are required on each of these signals. The following GMCH signal groups list the five possible GMBUS pairs. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 126: Leaving The Gmch Dvob Or Dvoc Port Unconnected
Pull-down resistors are required for the following signals if not used: DVOBFLDSTL DVOCFLDSTL DVOBCCLKINT Pull-up resistors are required for the following signals if not used: DVOBCINTR# ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 127: Miscellaneous Input Signals And Voltage Reference
DVODETECT: Leave unconnected (NC) when using the DVOB or DOVC port. AGPBUSY#: Connect directly to ICH4-M. A 10-k, pullup resistor is required, unless using 852PM platform or 852GME platform with external graphics DVORCOMP is used to calibrate the DVOB buffers. It should be connected to ground via a 40.2-...
Page 128: Agp Port Design Guidelines
The low-voltage operation on AGP (1.5 V) requires even more noise immunity. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 129: Agp Interface Signal Groups
GC/BE_[3:0]# signals are running at 2X GPIPE# GSBSTB# mode. GREQ# GAD_[31:0] signals and associated GC/BE_[3:0]# signals are running at 4X GGNT# mode. GPAR GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GAD_[31:0] GC/BE_[3:0]# GADSTB_[1:0] ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 130: Agp Routing Guidelines
46. In addition to this maximum trace length requirement (refer to Table 46 and Table 47) these signals must meet the trace spacing and trace length mismatch requirements in Sections 8.2.1.2 and 8.2.1.3. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 131: Trace Spacing Requirements
(trace spacing) and line lengths. These routing rules are divided by trace spacing. In 1:2 spacing, the distance between the traces is two times the width of traces. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 132: Trace Spacing Requirements
AGP signals (and all other signals) by at least 15 mils (1:3). The strobe pair must be length matched to less than ± 0.1 inches (that is, a strobe and its compliment must be the same length within ± 0.1 inches). ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 133: Trace Length Mismatch Requirements
The strobe pair must be length matched to less than ± 0.01 inches (that is, a strobe and its compliment must be the same length within ± 0.01 inches). Table 49 shows the AGP 2.0 routing summary. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 134: Agp Clock Skew
The designer should evenly distribute placement of decoupling capacitors in the AGP interface signal field. Intel recommends that the designer use a low-ESL ceramic capacitor, such as with a 0603 body- type X7R dielectric. In order to add the decoupling capacitors within 70 mils of the GMCH/MCH and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor.
Page 135: Agp Interface Package Lengths
GAD19 GST_0 GAD20 GST_1 GAD21 GST_2 GAD22 GRBFB GAD23 GWBFB GAD24 GFRAMEB GAD25 GIRDYB GAD26 GTRDYB GAD27 GSTOPB GAD28 GDEVSELB GAD29 GREQB GAD30 GGNTB GAD31 GPAR ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 136: Agp Routing Ground Reference
AGP 2.0 Specification. Pull-ups are allowed on any signal except AD_STB[1:0]# and SB_STB#. The Intel chipset GMCH has no support for the PERR# and SERR# pins of an AGP graphics controller that supports PERR# and SERR#. Pull-ups to a 1.5-V source are required down on the motherboard in such cases.
Page 137: Table 51. Agp Pull-Up/Pull-Down Requirements And Straps
Pull-Up NOTES: 1. The Intel chipset GMCH has integrated pull-ups to ensure that these signals do not float when there is no add-in card in the connector. 2. The Intel chipset MCH-M does not implement the PERR# and SERR# signals. Pull-ups on the motherboard are required for AGP graphics controllers that implement these signals.
Page 138: Agp Vddq And Vcc
25 mils to reduce crosstalk and maintain signal integrity. 8.2.10. AGP Compensation The 852GME chipset MCH-M AGP interface supports resistive buffer compensation. For PCBs with characteristic impedance of 55 , tie the GRCOMP pin to a 40.2 ± 1% pull-down resistor (to ground) via a 10-mil wide, very short ( 0.5 inches) trace.
Page 139: Figure 49. Dpms Circuit
AGP Port Design Guidelines Figure 49. DPMS Circuit Q6D2 Q6D1 BSS138 BSS138 AGP_PIPE#_FET PM_SUS_CLK DPMS_CLK 7 19,37 DPMS_CLK +V12S 17,23,27,37,45 R6D7 100K AGP_TY PEDET# ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 140: Hub Interface
The GMCH and ICH4-M pin-map assignments have been optimized to simplify the hub interface routing between these devices. Intel recommends that the hub interface signals be routed directly from the GMCH to the ICH4-M with all signals referenced to VSS. Layer transitions should be kept to a minimum.
Page 141: Hub Interface Data Hl[10:0] And Strobe Signals
1.5” 6” ± 100 Differential HLSTB pair HLSTB 1.5” 6” ± 100 Data lines HLSTB and HLSTB# must HLSTB# be ± 10 mils of each other ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 142: Table 55. Hub Interface Package Lengths For Ich4-M
Table 56. Hub Interface Package Lengths for GMCH Signal Pin Number Package Length (mils) HL[0] HL[1] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HL[10] GCLKIN HLSTB HLSTB# ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 143: Terminating Hl[11]
(< 10-15 mV). If the trace length exceeds 4 inches, then the locally generated voltage reference divider should be used. See Section 9.3.2 for the more details. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 144: Locally Generated Voltage Reference Divider Circuit
1% tolerance (see Table 59). Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV). If the voltage specifications are not met then individually generated voltage divider circuit for HIVREF and HI_VSWING is required. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 145: Single Gmch And Ich4-M Voltage Generation / Separate Divider Circuit For Vswing/Vref
C2, C5 = 0.01 µF (near component) HI_VSWING R6 = 78.7 VCCHI=1.5 V C1 = 0.1 µF (near divider) (800 mV) R7 = 24.2 C4, C6 = 0.01 µF (near component) ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 146: Separate Gmch And Ich4-M Voltage Generation / Separate Divider Circuits For Vref And Vswing
HI power pins. Similarly, if layout allows, metal fingers running on the V HI side of the board should connect the groundside of the capacitors to the V power pins. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 147 Hub Interface This page intentionally left blank. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 148: I/O Subsystem
10.1. IDE Interface This section contains guidelines for connecting and routing the Intel 82801DBM ICH4-M IDE interface. The ICH4-M has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels.
Page 149: Primary Ide Connector Requirements
The 10-k resistor to ground on the PDIAG#/CBLID# signal is required on the Primary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 150: Secondary Ide Connector Requirements
The 10-k resistor to ground on the PDIAG#/CBLID# signal is required on the Secondary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 151: Mobile Ide Swap Bay Support
IDE channels, respectively. By default, these bits are set to 0 and during normal power up, should be set to 1 by the BIOS to enable IORDY assertion from the IDE device when an access is requested. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 152: S5/G3 To S0 Boot Up Procedures For Ide Swap Bay
3. Once the system IDE interface is configured for normal operation once again, the reset signal to the swap device should be de-asserted to allow the drive to initialize. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 153: Pci
I/O Subsystem 10.2. The Intel 82801DBM ICH4-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2.2. The implementation is optimized for high performance data streaming when the ICH4-M is acting as either the target or the initiator in the PCI bus.
Page 154: Figure 58. Intel 82801Dbm Ich4-M Ac'97 - Codec Connection
If a modem codec is configured as the primary AC-link Codec, there should not be any Audio Codecs NOTE: residing on the AC-link. The primary codec may be connected to AC_SDIN0 as documented in the Intel ICH4-M Datasheet. Clocking is provided from the primary codec on the link via AC_BIT_CLK, and is derived from a 24.576-MHz crystal or oscillator.
Page 155: Figure 59. Intel 82801Dbm Ich4-M Ac'97 - Ac_Bit_Clk Topology
I/O Subsystem AC_SDIN1, and AC_SDIN2 may not be driven. If the link is enabled, the assumption can be made that there is at least one codec. Figure 59. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology ® Intel ICH4 AC_BIT_CLK Primary Codec Table 61.
Page 156: Figure 61. Intel 82801Dbm Ac'97 - Ac_Sdin Topology
(CS4205b). Results showed that if the AD1885 codec was used a 33- resistor was best for R1 and if the CS4205b codec was used a 47- resistor for R1 was best. 2. Bench data shows that a 47- resistor for R1 is best for the Sigmatel* 9750 codec. Figure 61. Intel 82801DBM AC’97 – AC_SDIN Topology Codec ®...
Page 157: Ac'97 Routing
These recommendations are not the only implementation or a complete checklist, but they are based on the ICH4-M platform. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 158: 10.3.2.1. Valid Codec Configurations
(R ), and the ICH4-M’s integrated pull-down resistor will be read as logic high (0.5 * VCC3_3 to VCC3_3 + 0.5 V). ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 159: Usb 2.0 Guidelines And Recommendations
Crossing over anti-etch (plane splits) increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with USB 2.0 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 160: 10.4.1.2. Usb 2.0 Trace Separation
The USBRBIAS pin and the USBRBIAS# pin can be shorted and routed 5 on 5 to one end of a 22.6 ±1% resistor to ground. Place the resistor within 500 mils of the ICH4-M and avoid routing next to clock pins. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 161: 10.4.1.4. Usb 2.0 Termination
1. These lengths are based upon simulation results and may be updated in the future. 2. All lengths are based upon using a common-mode choke (see Section 10.4.4.1 for details on common-mode choke). ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 162: Plane Splits, Voids, And Cut-Outs (Anti-Etch)
If the system fuse is rated at 1 amp, then the power carrying traces should be wide enough to carry at least 1.5 amps. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 163: Emi Considerations
Common mode chokes with a target impedance of 80 to 90 at 100 MHz generally provide adequate noise attenuation. Finding a common mode choke that meets the designer’s needs is a two-step process: ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 164: Esd
I/O APIC (I/O Advanced Programmable Interrupt Controller) The Intel ICH4-M is designed to be backwards compatible with a number of the legacy interrupt handling mechanisms as well as to be compliant with the latest I/O (x) APIC architecture. In addition to...
Page 165: Smbus 2.0/Smlink Interface
Both the SMBus host controller and the SMBus slave interface obey the SMBus 1.0 protocol, so the two interfaces can be externally wire-OR’ed together to allow an external management ASIC (such as Intel 82562EM 10/100 Mbps platform LAN connect) to access targets on the SMBus as well as the ICH4-M slave interface.
Page 166: Smbus Architecture And Design Considerations
SMbus-SMlink_IF Intel does not support external access of the ICH4-M’s Integrated LAN controller via the SMLink interface. Also, Intel does not support access of the ICH4-M’s SMBus slave interface by the ICH4-M’s SMBus host controller. Refer to the Intel ®...
Page 167: 10.6.1.2. General Design Issues/Notes
2. The maximum bus capacitance that a physical segment can reach is 400 pF. 3. The Intel ICH4-M does not run SMBus cycles while in S3. 4. SMBus devices that can operate in S3 must be powered by the V supply.
Page 168: Table 67. Bus Capacitance Reference Chart
100 to 200 pF 4.7 k to 1.2 k 200 to 300 pF 3.3 k to 1.2 k 300 to 400 pF 2.2 k to 1.2 k ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 169: Fwh
ICH4-M FWH signal INIT#. Trace lengths and resistor values can be found in Table 5. The voltage translator circuitry is shown in Figure 16. Intel strongly recommended that any system that implements a FWH should have its INIT# input connected to the ICH4-M.
Page 170: Fwh Vpp Design Guidelines
FWH INIT# Assertion/Deassertion Timings Due to the large routing solution space and necessity of a voltage translator in the design of a FWH on 852GME/852GMV/852PMand ICH4-M based platforms, the following timing requirements must be met to ensure proper system operation.
Page 171: Rtc
I/O Subsystem 10.8. The Intel 82801DBM ICH4-M contains a real time clock (RTC) with 256 bytes of battery backed SRAM. The internal RTC module provides two key functions: keeping date and time and storing system data in its RAM when the system is powered down.
Page 172: Rtc Crystal
I/O Subsystem 10.8.1. RTC Crystal The Intel 82801DBM ICH4-M RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls. Figure 72 documents the external circuitry that comprises the oscillator of the ICH4-M RTC.
Page 173: External Capacitors
(+23 ppm) but this configuration of C makes the circuit oscillate ° closer to 32.768 kHz at 0 C. The 6.8-pF value of C1 and 2 is the practical value. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 174: Rtc Layout Considerations
To do this, the diodes are set to be reverse biased when the system power is not available. Figure 73 is an example of a diode circuit that is used. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 175: Rtc External Rtcrst# Circuit
When RTCRST# is asserted, bit 2 (RTC_PWR_STS) in the GEN_PMCON_3 (General PM Configuration 3) register is set to 1, and ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 176: Vbias Dc Voltage And Noise Measurements
10.9. Internal LAN Layout Guidelines The Intel 82801DBM ICH4-M provides several options for LAN capability. The platform supports several components depending upon the target market. Available LAN components include the Intel ®...
Page 177: Footprint Compatibility
10.9.1. Footprint Compatibility The Intel 82540EP Gigabit Ethernet Controller and the Intel 82551QM Fast Ethernet Controller are all manufactured in a footprint compatible 15 mm x 15 mm (1-mm pitch), 196-ball grid array package. Many of the critical signal pin locations on the 82540EM and the 82551QM are identical, allowing designers to create a single design that accommodates any one of these parts.
Page 178: Intel 82801Dbm Ich4-M - Lan Connect Interface Guidelines
Direct point-to-point connection between the ICH4-M and the LAN component LOM Implementation 10.9.2.1.1. LOM (LAN On Motherboard) Point-To-Point Interconnect The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET is uniquely installed. Figure 76. Single Solution Interconnect LAN_CLK ®...
Page 179: 10.9.2.2. Signal Routing And Layout
The following are some general guidelines that should be followed. Intel recommends that the board designer simulate the board routing to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk.
Page 180: 10.9.2.5. Line Termination
For a noise free and stable operation, place the crystal and associated discrete components as close as possible to the Intel 82562ET/EM, keeping the trace length as short as possible and do not route any noisy signals in this area.
Page 181: 10.9.3.3. Intel 82562Et / Intel 82562Em Termination Resistors
± 1% receive differential pairs (RDP/RDN) should be placed as close to the Platform LAN connect component (Intel 82562ET or Intel 82562EM) as possible. This is due to the fact these resistors are terminating the entire impedance that is seen at the termination source (i.e. Intel 82562ET), including the wire impedance reflected through the transformer.
Page 182: Distance From Magnetics Module To Rj-45 (Distance A)
If the Intel 82562ET must be placed further than a couple of inches from the RJ-45 connector, distance B can be sacrificed. Keeping the total distance between the Intel 82562ET and RJ-45 will as short as possible should be a priority.
Page 183: 10.9.3.5.1. Terminating Unused Connections
10.9.3.5.2. Termination Plane Capacitance Intel recommends that the termination plane capacitance equal a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused pairs of the RJ-45. Pads may be placed for an additional capacitance to chassis ground, which may be required if the termination plane capacitance is not large enough to pass EFT (Electrical Fast Transient) testing.
Page 184: Intel 82562Et/Em Disable Guidelines
Intel® 82562EM/ET Disable 10K 5% There are four pins that can put the Intel 82562ET/EM controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. Table 73 describes the operational/disable features for this design. The four control signals shown in the below table should be configured as follows: Test_En should be pulled-down thru a 100- resistor.
Page 185: General Intel 82562Et/82562Em/82551Qm/82540Ep Differential Pair Trace Routing Considerations
82540EP/82541EI & 82562EZ(EX) Dual Footprint Design Guide Application Note (AP-444) (Reference# 12504) 10.9.6. General Intel 82562ET/82562EM/82551QM/82540EP Differential Pair Trace Routing Considerations Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes.
Page 186: 10.9.6.1.1. Trace Geometry And Length
Physically group together all components associated with one clock trace to reduce trace length and radiation. Isolate I/O signals from high speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 187: 10.9.6.1.3. Magnetics Module General Power And Ground Plane Considerations
Physically locate grounds between a signal path and its return. This will minimize the loop area. Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times contain many high frequency harmonics, which can radiate EMI. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 188: Common Physical Layout Issues
This does not take into account edge-to-edge capacitive coupling between the two traces. When the ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 189: Power Management Interface
If an ITP700FLEX debug port is implemented on the system, Intel recommends that the DBR# signal of the ITP interface be connected to SYS_RESET# as well. If SYS_RESET# is implemented, a weak pull-up resistor pulled-up to the 3.3-V standby rail (VccSUS3_3) should also be implemented to...
Page 190: Cpu Cmos Considerations
10.11. CPU CMOS Considerations The Intel 82801DBM ICH4-M has been designed to be voltage compatible with the CMOS signals of the Mobile Intel Pentium 4 processor and Intel Celeron processor. For these processor-based systems, the ICH4-M’s V_CPU_IO rail uses the same 1.05-V voltage as the V rails for the processor.
Page 191: Figure 85. Ich4-M Cpu Cmos Signals With Cpu And Fwh
I/O Subsystem Figure 85. ICH4-M CPU CMOS Signals with CPU and FWH V_CPU_IO @ 1.05 V FERR# Processor Output Signals ICH4-M ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 192 I/O Subsystem This page intentionally left blank. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 193: Platform Clock Routing Guidelines
Table 74 below provides a breakdown of the various individual clocks. Note: When used in 852GME /852PM platforms, the CK408 is configured in the unbuffered mode and a host clock swing of 710 mV. Table 74. Individual Clock Breakdown...
Page 194: Figure 86. Clock Distribution Diagram
DOT CLK SSCCLK PCICLK PCI Slot0 100/133MHz PCICLK PCI Slot1 Outputs PCICLK PCI Slot2 CLK33 CLK33 CK408 66MHz CLK33 48MHz 14MHz CLK66 ICH4 CLK14 Clock Distribution USBCLK ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 195: Clock Group Topologies And Routing Constraints
The recommended value for Rs is 33 ± 5%. Simulations have shown that Rs values above 33 provide no benefit to signal integrity but only degrade the edge rate. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 196: Table 75. Host Clock Group Routing Constraints
1. Differential pairs should be routed as a closely coupled side-by-side pair on a single layer over their entire length. 2. To minimize skew, Intel recommends that all clocks be routed on a single layer. If clock pairs are to be routed on multiple layers, the routed length on each layer should be equalized across all clock pairs.
Page 197: 11.2.1.1. Host Clock Group General Routing Guidelines
Platform Clock Routing Guidelines As specified in the table above, the nominal length of the clock pair terminating at the 852GME GMCH should be routed 0.25 inches shorter than the other two clock pairs. This is to compensate for a difference in package length between the CPU and the GMCH.
Page 198: Clk66 Clock Group
The length of this clock should be set within the range and then used as the basis for defining the length of all other length matched clocks. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 199: Host Clock To Clk66 Routing Recommendations
Trace length difference between BCLK and GCLKIN routing. Board manufacturing variations affecting signal delay across clock traces. All relevant variables should be evaluated over the system’s full specified operating temperature range. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 200: Clk33 Clock Group
Breakout Region Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 201: Pci Clock Group
5 mil trace with 5 mil space on outers Breakout Region Exceptions 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 202: Clk14 Clock Group
Breakout Region Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 203: Dotclk Clock Group
0.5-inch intervals. 2. If external graphics is only supported on the platform then dotclock does not need to be connected to GMCH. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 204: Sscclk Clock Group
4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” If external graphics is only supported on the platform then dotclock does not need to be connected to GMCH. NOTE: ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 205: Usbclk Clock Group
5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” 11.3. CK-408 Clock Power Supply Decoupling See Section 12.7.8 for details. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 206: Pwrdwn# Signal Connections
Also SLP_S3# can help reduce power consumption because it will be asserted before the 3.3-V supply will be shut off, thus minimizing the amount of time that the clocks will be left toggling. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 207: Platform Power Delivery Guidelines
Full-On and the S1M (CPU Stop-Grant state). Suspend operation. During suspend operation, power is removed from some components on the motherboard. 852GME chipset-based systems can be designed to support a number of suspend states such as Power-On-Suspend (S1M), Suspend-to-RAM (S3), Suspend-to-Disk (S4), and Soft- Off (S5).
Page 208: Platform Power Requirements
Platform Power Requirements Figure 96 below shows the power delivery architecture for an example 852GME/852GMV/852PMchipset platform. This power delivery architecture supports the “Instantly Available PC Design Guidelines” via the S3 system state. To ensure that enough power is available during S3, a thorough power budget should be completed. The power requirements should include each device’s power requirements, both in suspend and in Full-On.
Page 209: Voltage Supply
+V*S Clocks FULL ON HIGH HIGH HIGH HIGH S1M (POS) HIGH HIGH HIGH S3 (STR) HIGH HIGH ON/OFF S4 (STD) HIGH ON/OFF S5 (Soft Off) ON/OFF ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 210: Power Supply Rail Descriptions
+VCC_VID -HIGH See IMVP-V Design Guide for detail +VCCP IMVP-V IMVP-V +VCC_VID See IMVP-V Design Guide for detail +VCC_VID IMVP-V VR_ON See IMVP-V Design Guide for detail ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 211: 852Gme/852Gmv/852Pmgmch/Ich4-M Platform Power-Up Sequence
Platform Power Delivery Guidelines 12.4. 852GME/852GMV/852PMGMCH/ICH4-M Platform Power-Up Sequence Figure 97 describes the power-on timing sequence for a GMCH / ICH4-M-based platform. Figure 97. GMCH / ICH4-M Platform Power-Up Sequence System S0 state State Hub interface "CPU Reset Complete" message...
Page 212: Table 85. Timing Sequence Parameters For Figure 97
2. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs. 3. This transition is clocked off the 66-MHz CLK66. 1 CLK66 is approximately 15 ns. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 213: Ich4-M Power Sequencing Requirements
0.7 V. It must also power down after or simultaneous to V . These rules must be followed in order to ensure the safety of the Intel ICH4-M. If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the V rail.
Page 214: Design Guidelines
ICH4-M ICH4-M Customer specific or Customer specific or USB D+ USB D+ Intel recommended Intel recommended USB interface USB interface USB D- USB D- circuits circuits ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 215: Gmch Power Sequencing Requirements
12.4.2. GMCH Power Sequencing Requirements No GMCH power sequencing requirements exist for the 852GME / 852PM GMCH platform. All GMCH power rails should be stable before deasserting reset, but the power rails can be brought up in any order desired. Good design practice would have all GMCH power rails come up as close in time as possible, with the core voltage coming up first.
Page 216: Pwr Ich4-M Sys_Reset# Signal
PWR ICH4-M SYS_RESET# Signal The Intel ICH4-M has a new signal called ICH4-M SYSRST#. This signal is an input to the ICH4-M and provides a way to activate a system reset. In previous designs with ICH3-M, system reset logic was often tied into PWROK, forcing an asynchronous reset.
Page 217: Ddr Interface Decoupling Guidelines
This via should be as close to the capacitor pad as possible, within 25 mils, and with as thick a trace as possible. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 218: 12.5.1.2. Ddr So-Dimm System Memory Decoupling Guidelines
If this states a tolerance in terms of volts (e.g. VREF says ± 0.025 V), then that specific voltage tolerance should be used, not a percentage of the measured value. Likewise, ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 219: Table 88. Absolute Vs. Relative Voltage Specification
Volts, V Vdd/2 + 0.05 V Vdd/2 – 0.05 Vdd/2 Vdd/2 + 0.05 Reference Supply Voltage, Static I/O Reference Iref Amperes, A < 0.001 Supply Current, Static ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 220: 12.5.3.1. Smvref Layout And Routing Recommendations
12.5.3.1. SMVREF Layout and Routing Recommendations There is one SMVREF pin on the 852GME / 852PM GMCH that is used to set the reference voltage level for the DDR system memory signals (SMVREF_0). The reference voltage must be supplied to the SMVREF pin.
Page 221: Table 92. Gmch System Memory I/O Smvref Calculation
5. The implementation of a buffer is also required by the DDR. The same VREF may be used for both GMCH and the DDR as well. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 222: 12.5.3.2. Ddr Vref Requirements
Therefore, the use of a buffer is highly recommended for these reference voltage requirements. 12.5.4. DDR SMRCOMP Resistive Compensation The 852GME / 852PM GMCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer characteristics to specific board and operation environment characteristics. Refer to the Intel ® ®...
Page 223: Ddr Vtt Termination
Resistor packs and ± 5% tolerant resistors are acceptable for this application. Only signals from the same DDR signal group can share a resistor pack. See Section 12.5.1 and Section 12.7 for details on high frequency and bulk decoupling requirements. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 224: Clock Driver Power Delivery Guidelines
Layer 2. (Assuming top trace is Layer 1.) Intel also recommends that a ground flood be placed directly under the clock chip to provide a low impedance connection for the VSS pins.
Page 225: Figure 105. Decoupling Capacitors Placement And Connectivity
/ 3V66_2 48 MHz 66Buf 3V66_1 / f1 / 3V66_ 3 66Buf PCI_Sto f2 / 3V66_ 66In / 3V66 3V66_5 PWRD VddA SDAT Vtt_Pwr gd # ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 226: Decoupling Recommendations
12.7. Decoupling Recommendations Intel recommends proper design and layout of the system board bulk and high frequency decoupling capacitor solution to meet the transient tolerances for each component. To meet the component transient load steps, it is necessary to properly place bulk and high frequency capacitors close to the component power and ground pins.
Page 227: Intel Ich4-M Decoupling Guidelines
12.7.3. Intel ICH4-M Decoupling Guidelines The Intel ICH4-M is capable of generating large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below specified limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins.
Page 228: Ddr Vtt High Frequency And Bulk Decoupling
Layer 1 4.5 mils nominal Layer 2 48 mils nominal Layer 3 Layer 4 Current Flow to Decoupling Cap Table 98. Decoupling Requirements for the Intel ICH4-M Decoupling Decoupling Type (Pin type) Decoupling Placement Requirements VCC3_3 (6) 0.1 µF Decoupling Cap (Vss)
Page 229: Hub Interface Decoupling
Three 0.1-µF high frequency decoupling caps in a 0603 package placed close to the VDDA pins on the CK-408. One 10-µF bulk decoupling cap in a 1206 package placed close to the VDDA generation circuitry ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 230: Intel 852Gme/852Gmv/852Pmgmch Analog Power Delivery
Platform Power Delivery Guidelines 12.8. Intel 852GME/852GMV/852PMGMCH Analog Power Delivery 12.8.1. Analog Supply Filter Requirements Table 99 summarizes the eight analog circuits that require filtered supplies on the 852GME / 852PM GMCH. The analog circuits are: VCCASM VCCQSM VCCAHPLL VCCADPLLA...
Page 231: Recommended Routing/Component Placement
If possible, route a trace from the VSSADAC and VSSALVDS balls to the capacitor before terminating to ground. 12.9. Intel 852GME/852GMV/852PMMaximum Supply Current Numbers Table 100 shows the preliminary Intel 852GME / 852PM GMCH maximum supply current estimates. ® ® ® Intel...
Page 232: Intel Ich4-M Power Consumption Numbers
1.2 V DDR DLLs 0.40 A 2.5 V DDR 2.07 A 12.10. Intel ICH4-M Power Consumption Numbers Table 101 shows the preliminary Intel ICH4-M power consumption estimates. Table 101. Intel ICH4-M Power Consumption Measurements Power Plane Maximum Power Consumption S1-M S4/S5 1.5 V Core...
Page 233: Thermal Design Power
It does not represent the expected power generated by a power virus. The thermal design power numbers for the 852GME/ 52PM GMCH and Intel ICH4-M are listed below. Table 102. Intel 852GME/852GMV/852PMGMCH Component Thermal Design Power...
Page 234: Test Signals
13.1. Mobile Intel Pentium 4 Processor Reserved Signals The Mobile Intel Pentium 4 processor has NC and TESTHI signals that are Intel reserved in the pin- map. For connection recommendations on the TESTHI signals, refer to the latest Mobile Intel ®...
Page 235: Intel 852Gme / 852Pm Gmch Rsvd Signals
Intel 852GME / 852PM GMCH RSVD Signals The Intel 852GME / 852PM GMCH has a total of 32 RSVD and 12 NC signals that are Intel reserved in the pin-map. The recommendation is to provide test points for all RSVD signals. All NC signals should be left as no connects.
Page 236: Platform Design Checklist
This checklist provides design recommendation and guidelines for Intel 852GME/PM chipset platform for use with the Mobile Intel Pentium 4 processor and Intel Celeron processor. This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements the 852GME/PM chipset.
Page 237: Customer Implementation Of Voltage Rails
Fill in schematic name of voltage rails and mark boxes of when rails are powered on. Name of Rail On S0-S1 On S3 On S4 On S5 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 238: Design Checklist Implementation
Platform Design Checklist 14.3. Design Checklist Implementation The voltage rail designations in this design checklist are as general as possible. The following table describes the equivalent voltage rails in the Intel CRB schematics. Checklist Rail Intel CRB Rail On S0-S1...
Page 239 Platform Design Checklist Checklist Rail Intel CRB Rail On S0-S1 On S3 On S4 On S5 Notes Vcc1_25 +V1.25S [DDR_Vtt] VccCORE +VCC_CORE NOTES: 1. A rail powered in Sx is dependent on implementation. 2. VccLANx rail is powered on in Sx is dependent on implementation.
Page 240 Please refer to Figure 109 VCCIOPLL filter VCCSENSE, Connect to test vias VSSSENSE VSS[182:0] Connect to gnd NOTE: Default tolerance for resistors is ± 5% unless otherwise specified. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 241: Figure 108. Routing Illustration For Init
VCCA 10uH 33uF VSSA VCCIOP 10uH Processor Figure 110. Voltage Translation Circuit for PROCHOT# 3.3V 3.3V +/-5% 1.3K To Receiver +/-5% 3904 +/-5% From Driver 3904 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 242: In Target Probe (Itp)
Decoupling guidelines are recommendations based on our reference board design. Customers will need to NOTE: take layout & PCB board design into consideration when deciding on overall decoupling solution. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 243: Power-Up Sequence
Processor Datasheet. See Figure 111. Please refer to the PWRGOOD active to RESET# inactive Processor Datasheet. See Figure 111. Please refer to latest processor datasheet. NOTE: ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 244: Figure 111. Mobile Intel Pentium 4 Processor Power Up Sequence
Platform Design Checklist Figure 111. Mobile Intel Pentium 4 Processor Power Up Sequence ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 245: Clock Checklist
LPC. Each receiver requires one 33- ohm series resistor. SEL[2] 1 k-20 k pull-down to gnd SEL[1] 330 k-20 k pull- up to Connects to proceesor BSEL[0] Vcc3_3 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 246: Figure 112. Clock Power-Down Implementation
When using external graphics, may replace series resistor with 100- resistor because signal is not needed. NOTE: Figure 112. Clock Power-down Implementation VccSus3_3 PM_SLP_S1# CLK_PWRDWN# PM_SLP_S3# ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 247: 852Gme/852Gmv/852Pmchecklist
SCS#[3:0] SDQ[63:0], pull-up to Vcc1_25 SDM[7:0], SDQS[7:0] SDQ[71:64], pull-up to Vcc1_25 For 852GME, if ECC support is not SDM8, SDQS8 implemented, SDQ[71:64], SDM8, and SDQS8 should be left as NC. For ECC support, these signals connect to SO- DIMMs. SMA[12:6,3,0]...
Page 248: 14.8.1.2. Ddr So-Dimm Interface
Power must be provided during S3. VDDSPD Connect to Vcc3_3 SA[2:0] Connect to either VC3_3 or These lines are used for strapping the SPD address for each SO-DIMM. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 249 Signal can be left as NC (“Not Connected) DU[4:1] Signal can be left as NC (“Not Connected) GND[1:0] Signal can be left as NC (“Not Connected) ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 250: So-Dimm Decoupling Recommendation
1% pull-up to VCC Signal voltage level = 2/3 of VCC. Need one 0.1 µF cap and one 1 µF cap for voltage divider. 1% pull-down to gnd Figure 114. 852GME HXSWING & HYSWING Reference Voltage Generation Circuit +VCC +VCC 301R1a...
Page 251: Hub Interface
100 k pull-down to gnd Pull-down resistor required only if signal is unused (10 k-100 k). It is up to DVO device to drive this signal. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 252 GAD0/DVOBHSYNC GAD1/DVOBVSYNC GBCE#1/DVOBBLANK# GAD30/DVOBFLDSTL (pin 100 k pull-down to gnd For 852GME, pull-down resistor required on this signal (10 k-100 k). If AGP has been used pin doesn’t require pull-down. GIRDY/MI2CCLK, 2.2 k pull-up to Vcc1_5 Pull-up resistor required on each signal even if GDEVSEL/MI2CDATA they are unused (2.2 k-100 k).
Page 253: Figure 115. Dpms Clock Implementation
Isolation circuit is needed for normal operation. See Figure 116. Figure 115. DPMS Clock Implementation Vcc1_5 To GMCH PM_SUS_CLK DPMS pin From ICH4-M BSS138 SUS_CLK SUSCLK ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 254: Figure 116. Q-Switch Circuit
Platform Design Checklist Figure 116. Q-SWITCH Circuit ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 255: Dac
GMCH and VGA connector. 1% pull-down to gnd, 3.3 100 MHz pF cap to gnd, ESD diode See latest Intel Customer Reference Schematics for more details. protection for Vcc1_5 When using external graphics, the 75 On VGA side of ferrite bead: 1% pull-down to gnd is not needed.
Page 256: Miscellaneous
200 MHz 533 MHz 266 MHz 133 MHz 266 MHz 533 MHz 333 MHz 166 MHz 266 MHz 400 MHz 333 MHz 166 MHz 250 MHz ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 257: Gmch Decoupling Recommendations
0.1 µF Bulk decoupling is based on VR solutions used on CRB design. 10 µF VCCAHPLL Connect to VCC1_5S 0.1 µF VCCAGPLL Connect to VCC1_5S 0.1 µF ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 258: Gmch Power-Up Sequence
852PM Chipset MCH Datasheet. ® RSTIN# inactive to CPURST# inactive. Please refer to Intel 852GME ® Chipaer GMCH and Intel 852PM Chipset MCH Datasheet. Figure 117. 852GME Power-up Sequence CPURST# 1ms max RSTIN# 1ms min PWROK GMCH PWR Rails ® ®...
Page 259: Ich4-M Checklist
8.2 k pull-up to Vcc3_3 External pull up is required for INT_PIRQE#/GPIO2 INT_PIRQ#[A:D]. External pull up is INT_PIRQF#/GPIO3 required when muxed signal INT_PIRQG#/GPIO4 (INT_PIRQ[E:H]#/ GPIO[2:5]) is ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 260 Platform Design Checklist Pin Name System Pull-up /Pull- Notes down INT_PIRQH#/GPIO5 implemented as PIRQ. INT_SERIRQ 8.2 k pull-up to Vcc3_3 ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 261: Gpio
GPIO[34] can be used as SER_EN. GPIO[35] can be used as FWH_WP#. GPIO[36] can be used as FWH_TBL#. GPIO[40] can be used as IDE_PATADET. GPIO[41] can be used as IDE_SATADET. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 262: Agp_Busy# Design Requirement
This ICH4-M signal must be connected to the AGP_BUSY# output of GMCH. When using external graphics, AGP_BUSY# may be left as NC to the GMCH. Please also consult Intel for the latest AGP Busy and Stop signal implementation. NOTE: 14.9.4. (SMBus) System Management Interface...
Page 263: Ac '97 Interface
A series termination resistor is required for the PRIMARY CODEC. One series termination resistor is required for the SECONDARY/ TERTIARY CODEC connector card if the resistor is not found on the connector card. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 264: Ich4-M Power Management Interface
10 k pull-up to V3ALWAYS This signal to ICH4-M should not float. It needs to be at valid level all the time. if not actively driven. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 265: Fwh/Lpc Interface
Figure 119 and Figure 120 HUB_VSWING signal voltage level = 0.80 V ± 8%. Three options are available for generating these references. HUB_PD11 pull-down to gnd ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 266: Figure 118. Separated Gmch And Ich4-M Vswing/Vref Reference Voltage Circuit
Figure 118. Separated GMCH and ICH4-M VSWING/VREF Reference Voltage Circuit VCC_GMCH_Hub = 1.5V 86.6_1% PVSWING 100_1% GMCH VCC_GMCH_Hub = 1.5V HLVREF VCC_ICH_Hub = 1.5V 130_1% HUB_VSWING 150_1% ICH4-M VCC_ICH_Hub = 1.5V HUB_VREF ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 267: Figure 119. Single Or Locally Generated Gmch & Ich4-M Hivref/Hi_Vswing
R7 = 24.2 Ω ± 1% C1 and C3 = 0.1 µF PVSWING (near divider) HI_VSWING C2, C4, C5, C6 = Intel ® HLVREF HIREF 0.01µF (near (G)MCH ICH4 component) ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 268: 14.9.10. Rtc Circuitry
3.3V Sus is Active Whenever System Plugged In RTCX1 is the Input to the Internal Oscillator Vbatt is Voltage Provided By Battery RTCX2 is the feedback for the external crystal ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 269: 14.9.11. Lan Interface
4.7K pull-up This signal has integrated series resistor in ICH4-M. to Vcc3_3 IDE_PRST# 22-47 The signal must be buffered to provide IDE_RST# for improved signal integrity. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 270: 14.9.13. Secondary Ide Interface
(0.5 * Vcc3_3 to Vcc3_3 + 0.5) ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 271: 14.9.15. Ich4-M Decoupling Recommendations
PCB board design into consideration when deciding on their overall decoupling solution. Capacitors should be place less than 100 mils from the package. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 272: 14.9.16. Ich4-M Power-Up Sequence
Similarly, if PM_VGATE is asserted after PWROK, it must be delayed 3-10 ms from PWRGD from the VR (which enables clock). 5. Please refer to ICH4-M for latest specifications. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 273: Figure 122. Ich4 Power-Up Sequence Waveforms
PM_VGATE, it must be delayed 3-10 ms from PWRGD from the VR (which enables clock). Similarly, if PM_VGATE is asserted after PWROK, it must be delayed 3-10 ms from PWRGD from the VR (which enables clock). ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 274: Usb Power Checklist
Port 100-150uF Switch G G n n d d Ferrite Bead V V c c c c 470pF Port 100-150uF G G n n d d ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 275: Fwh Checklist
On CRB, the power monitoring logic waits for PM_PWROK to go high before deasserting this signal to enable the LAN device. It also keeps this signal high during S3. See Figure 124. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 276: 14.12.2. Decoupling Recommendations
VCCT[4:1] 4.7 uH from power supply to VCCR[2:1] Connect to 0.1 µF VccSus3_3LAN via filter 4.7 µF VCCR pins. Caps on VCCR side of the inductor. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 277: Schematics
Schematics Schematics Refer to the following pages for schematics. ® ® ® Intel 852GME, Intel 852GMV and Intel 852PM Chipset Platforms Design Guide...
Page 278 Intel® 852GME Platform with the Mobile Intel® Pentium® 4 Processor, Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading Technology on 90-nm process technology, Intel® Celeron® Processor and Intel® Celeron® D Processor Customer Reference Board Mobile Intel Proc Pentium 4 CK-408 Test Points...
Page 279 CUSTOMER REFERENCE PLATFORM SCHEMATIC ANNOTATIONS AND BOARD INFORMATION Voltage Rails I C / SMB Addresses Default Jumper Settings +VDC Primary DC system power supply (10 to 21V) Device Address Jumper Default Option Description Page Clock Generator 1101 001x SMB_ICH_S J7B1 GMCH Strap: PSB Voltage +VCC_IMVP Core/VTT voltage for processor &...
Page 280 U2E1B H_ADS# H_A#16 A16# ADS# H_A#15 TP_CPU_AP0# A15# AP0# H_A#14 TP_CPU_AP1# U2E1A H_D#[15:0] A14# AP1# H_D#[47:32] 8 H_A#13 TP_CPU_BINIT# H_D#15 H_D#47 A13# BINIT# D15# D47# H_A#12 H_D#14 H_D#46 H_BNR# A12# BNR# D14# D46# H_A#11 H_D#13 H_D#45 A11# BPRI# H_BPRI# 8 D13# D45# H_A#10...
Page 281 U2E1E Processor-MobilSkt VSS1 VSS81 VSS2 VSS82 VSS3 VSS83 VSS4 VSS84 VSS5 VSS85 3,5,9,10,18,20,40,41,47,48 +VCC_IMVP VSS6 VSS86 VSS7 VSS87 VSS8 VSS88 VSS9 VSS89 U2E1D R2D3 VSS10 VSS90 VSS11 VSS91 VCC1 VCC52 AA11 VSS12 VSS92 VCC2 VCC53 AA13 VSS13 VSS93 VCC3 VCC54 AA15 AF15 VSS14...
Page 282 Processor Thermal Sensor 6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48 +V3.3S 6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48 +V3.3S Address Select Straps C3A9 R3B2 R2B2 Current Address: 0.1UF RP2A1D RP2A1B RP2A1C 1001 110x U3A1 R3A7 STBY# STBY# H_THERMDA_D H_THERMDA SMB_THRM_DATA 32,37 SMBDATA ADD0 C3A10 ADD0 SMBCLK SMB_THRM_CLK 32,37 R3B1 2200PF ADD1 THRM_ALERT# ADD1 ALERT# H_THERMDC_D...
Page 283 5,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48 +V3.3S +V3.3S_CLKRC J3F2 R2F7 FB2F1 +V3.3S_CLKVDD 300ohm@100MHz C2F4 C2U6 C2F3 C3U1 C3U3 C2U2 C2U3 C3U2 0.01_1% C2U4 C2U5 Place 0ohm near 22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF crystal. NO_STUFF_SMA CON R3F18 FB2F3 Place crystal within 500 NO_STUFF_0 +V3S_CLKVDDA 14.318MHZ...
Page 284 MCH_SMVSWINGL 10 8,15 AGP_ST1 GST[1] TP_MCH_NC9 AJ19 AJ29 MCH_SMVSWINGH 10 SMVSWINGH 8,15 AGP_ST0 GST[0] TP_MCH_NC10 AGP_WBF# GWBF# NC10 TP_MCH_NC11 C5F13 852GME C5F6 C5F5 AGP_RBF# GRBF# NC11 TP_RSVD10 RVSD4 0.1UF 0.1UF 0.1UF AGP_CBE#2 GCBE#[2] 852GME Title GMCH (1 of 3) Size Project:...
Page 285 H_RS#1 HLSTB RS1# C4E5 C4E6 C5T8 10,18 HUB_PSTRB# H_RS#2 HLSTB# RS2# HUB_HLZCOMP HLRCOMP 0.1UF 0.1UF MCH_PSWING PSWING 10,47 MCH_HLVREF HLVREF Title C6T1 C6T2 852GME GMCH (2 of 3) 0.1UF 0.1UF Size Project: Document Number Date: Friday, May 21, 2004 Sheet...
Page 286 L6F1 VSS73 VSS158 VCCGPIO_1 VCCASM0 +V1.5S_GMCH_ASM R5R5 0.01_1% AJ27 VSS74 VSS159 VCCASM1 AC28 C5D4 VSS75 VSS160 C5D1 C5R3 C5D17 C5D10 852GME C6E14 AE28 VSS76 VSS161 C6E13 VSS77 VSS162 47uF 22UF 0.1UF 0.1UF 0.1UF 0.1UF 100uF VSS78 VSS163 AB15 VSS79 VSS164...
Page 287 LAI Hub Interface GMCH-GT Compensation & Reference Voltages 8,18 HUB_PD[10:0] J6U1 3,4,5,9,18,20,40,41,47,48 +VCC_IMVP 3,4,5,9,18,20,40,41,47,48 +VCC_IMVP NO_STUFF_HUBLINK Host MCH_HLVREF R5R9 R4T1 301_1% 301_1% R6E8 HUB_PD0 LAI_HUB_PIN6 R6F4 392_1% R5R10 R4E2 LAI_HUB_PIN7 HUB_PD1 392_1% 8,47 MCH_HXSWING 8,47 MCH_HYSWING HUB_PD2 LAI_HUB_PIN10 150_1% 150_1% R6F5 392_1% LAI_HUB_PIN11...
Page 288 5,6,8,9,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48 +V3.3S +V3.3S_SPD R4W1 0.01_1% Power plane for Serial Presence Detect logic 12,13,14 M_DATA_R_[63:0] M_AA_FR_0 J6H1A CON200_DDR-SODIMM M_AA_FR_0 M_DATA_R_0 M_AA1 M_AA2 M_DATA_R_1 12,43,47,48 +V2.5_DDR J6H1B CON200_DDR-SODIMM 7,14 M_AA[2:1] M_DATA_R_2 VDD1 VSS1 M_AA_FR_3 M_DATA_R_3 VDD2 VSS2 M_AA_FR_3 M_AA4 M_DATA_R_4 VDD3 VSS3 M_AA5 M_DATA_R_5 7,14...
Page 289 11,13,14 M_DATA_R_[63:0] M_AA0 J6H2ACON200_DDR-SODIMM_REV 7,13,14 M_AA0 M_DATA_R_0 M_AB1 11,43,47,48 +V2.5_DDR J6H2B CON200_DDR-SODIMM_REV M_DATA_R_1 M_AB2 7,14 M_AB[2:1] VDD1 VSS1 M_DATA_R_2 VDD2 VSS2 M_AA3 M_DATA_R_3 VDD3 VSS3 7,13,14 M_AA3 M_AB4 M_DATA_R_4 VDD4 VSS4 M_AB5 M_DATA_R_5 7,14 M_AB[5:4] VDD5 VSS5 M_AA6 M_DATA_R_6 VDD6 VSS6 M_AA7 M_DATA_R_7...
Page 290 M_DATA_R_[63:0] 11,12,14 M_DATA0 RP6G3D M_DATA_R_0 M_DATA32 RP5G11D 10 M_DATA_R_32 M_DATA1 M_DATA_R_1 M_DATA33 M_DATA_R_33 RP6G3C RP5G11C 10 7,12,14 M_AA[12:6] M_AA_FR_[12:6] 11 M_DATA2 M_DATA_R_2 M_DATA34 M_DATA_R_34 M_AA12 M_AA_FR_12 RP6G3A RP5G11A 10 RP5G14B 10 M_DATA3 M_DATA_R_3 M_DATA35 M_DATA_R_35 M_AA11 M_AA_FR_11 RP6G4D RP4G5D RP5G14C 10 M_DATA4 RP6G1D M_DATA_R_4...
Page 291 7,12,13 M_AA0 7,11 M_AA[2:1] 7,11,12 M_CKE0 43,47,48 +V1.25S 7,11,12 M_CKE1 7,12,13 M_AA3 M_CB_R[7:0] 11,12,13 7,11 M_AA[5:4] 7,11,12 M_CS0# 7,11,12 M_CS1# 7,12,13 M_AA[12:6] M_DATA_R_[63:0] M_DQS_R[8:0] 11,12,13 M_DATA_R_[63:0] 7,12,13 M_AA[12:6] 11,12,13 M_DQS_R[8:0] 7,12 M_CS2# 7,12 M_CS3# 7,12 M_CKE3 7,12 M_CKE2 Layout note: Place one cap close to every 2 pullup resistors terminated to +V1.25. 7,12,13 M_BS0# 7,12,13...
Page 292 5,19,20,21,22,23,27,28,29,32,36,37,38,39,44,48 +V3.3ALWAYS 9,19,20,44,47,48 +V1.5S Q6C2 Q6C4 BSS138 BSS138 J6C1 ADD 124 R6E4 2.2k AGP_PIPE#_FET 19,37 PM_SUS_CLK AGP_PIPE# 7 +V5S_AGP AGP_AD15 AGP_AD0 3.3Vaux AGP_AD1 5.0V2 AGP_PIPE# 17,23,27,37,38,44 +V12S R7E1 2.2k 17,23,27,37,38,44 +V12S AGP_AD2 5.0V1 AGP_DEVSEL# AGP_AD3 C6C6 AGP_AD4 R6D4 2.2k AGP_AD5 VCC3.3_1 R6C14 AGP_FRAME#...
Page 293 +V3.3S 5,6,8,9,11,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48 +V3.3S_LVDSDDC LVDS Interface R6N5 0.01_1% +V3.3S 5,6,8,9,11,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48 +V3.3S_LVDS R6N3 R6N4 J6B1 2.2k 2.2k R5N5 0.01_1% Q5B3 +V3.3S_LVDS_PANEL Test points for 24bpp support R5N3 C5N1 C5B7 C5B9 R6C2 LVDS_DDCPCLK LVDS_YAM3 100K 1000PF 0.1UF 22UF NO_STUFF_0 LVDS_DDCPDATA LVDS_YAP3 LVDS_YAM0 R5N4 LVDS_YAP0 LVDS_VDDEN_D# 100K...
Page 294 +V1.5S_GMCH_ADAC 15,23,27,37,38,44 +V12S 8,15,16,18,20,23,24,25,27,34,35,39,40,44,47 +V5S +V5S_F_DAC C6R2 C6R1 C6R3 F3A1 0.1UF 0.1UF 0.1UF CR6D1 ESD DIODE ARRAY R3A6 1.1A CR4M6 Q4M1 DDC_GATE DAC_RED 1N4148 I/O1 I/O6 DAC_GREEN R4A1 I/O2 I/O5 DAC_BLUE 100K I/O3 I/O4 4.7K R4M2 FB3A7 DDC_SRC 50OHM C4N1 R3M1 R4M1 0.1UF...
Page 295 3,4,5,9,10,20,40,41,47,48 +VCC_IMVP 5,6,8,9,11,16,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48 +V3.3S U7G2A 22,23,24 PCI_AD[31:0] SM_INTRUDER# SM_INTRUDER# 21,37 PCI_AD0 R8G9 PCI_AD0 SMLINK0 PCI_AD1 R8G8 PCI_AD1 SMLINK1 PCI_AD2 SMB_CLK R6W19 PCI_AD2 SMB_CLK SMB_DATA PCI_AD3 PCI_AD3 SMB_DATA PCI_AD4 FWH_INIT# 31 PCI_AD4 SMB_ALERT#/GPIO11 SMB_ALERT# 21,37 PCI_AD5 PCI_AD5 H_A20GATE 36 PCI_AD6 CR8G2B PCI_AD6 CPU_A20GATE CPU_A20M#...
Page 296 +V3.3 15,18,20,23,27,30,32,35,37,38,39,43,44 U7G2B GPIO7 R7J2 7,15 AGP_BUSY# PM_AGPBUSY#/GPIO6 GPIO_7 ICH_GPIO7 37 GPIO8 C2G11 R8W10 PM_SYSRST# PM_SYSRST# GPIO_8 SMC_EXTSMI# 32,34,36,37 U2G1 GPIO12 R7W1 32,36,37 PM_BATLOW# PM_BATLOW# GPIO_12 SMC_RUNTIME_SCI# 32,36,37 0.1UF GPIO13 R8W11 15,37 PM_C3_STAT# PM_C3_STAT#/GPIO21 GPIO_13 SMC_WAKE_SCI# 32,36,37 GPIO25 SLP_S1#_D R7Y2 21,22,23,24,32,34,37 PM_CLKRUN# AUDIO_PWRDN...
Page 297 +V1.5ALWAYS +V1.5A_ICH R8J7 U7G2C 19,21,22,24,37 +V3.3S_ICH +V3.3S 5,6,8,9,11,16,18,21,23,2 0.01_1% C6G1 C7W6 C7W15 C7W18 VCCSUS1.5_0 VCC3.3_0 R6H2 VCCSUS1.5_1 VCC3.3_1 10UF 0.1UF 0.1UF VCCSUS1.5_2 VCC3.3_2 NO_STUFF_0.1UF VCCSUS1.5_3 VCC3.3_3 +V1.5 No Stuff C7J3 C7J2 C7W2 C7W5 C7W10 C7W13 C7W17 C7W9 0.01_1% VCCSUS1.5_4 VCC3.3_4 R7G4 +V1.5_ICHLAN VCCSUS1.5_5...
Page 298 20,37 +V3.3ALWAYS_ICH 20,22,23,27,36,37,43,44 ICH4 Pullups RP8H6C +V3.3ALWAYS 5,15,19,20,22,23,27,28,29,32,36,37,38,39,44,48 19,35,37 PM_RI# RP8H7B 18,37 SMB_ALERT# +VDC 15,16,44 R5P7 +V5_ALWAYS Generation 19,20,22,24,37 +V3.3S_ICH 100K_1% RP8H2D 8.2K 18,22,23,24 PCI_FRAME# V5A_PWRGD RP8H3C 8.2K Vout=0.8(1+Rtop/Rbot) 18,22,23,24 PCI_IRDY# RP8H2C 8.2K Vout=0.8(1+(3.92k/750))= 4.98V 18,22,23,24 PCI_TRDY# RP8H2B 8.2K IMAX OUT = 50mV / 10mohms = 5A R5P6 18,22,23,24 PCI_STOP#...
Page 299 +V12S_PCI 23,44 -V12S 23,44 -V12S +V12S_PCI +V3.3ALWAYS 5,15,19,20,21,23,27,28,29,32,36,37,38,39,44,48 +V5S_PCI +V5_PCI +V3.3ALWAYS 5,15,19,20,21,23,27,28,29,32,36,37,38,39,44 +V5S_PCI +V3.3S_PCI +V5S_PCI +V5S_PCI -12V TRST# -12V TRST# +V5_PCI +V3.3S_PCI +12V +12V +V3.3S_PCI +V3.3S_PCI GND1 GND1 18,21,23 INT_PIRQG# 18,21,23 INT_PIRQF# +5V (1) +5V (7) +5V (1) +5V (7) 18,21,23 INT_PIRQE# +5V (2)
Page 300 5,15,19,20,21,22,27,28,29,32,36,37,38,39,44,48 +V3.3ALWAYS Moon ISA support J9E4 +V5_PCI 15,17,27,37,38,44 +V12S Default: 1-2 Moon ISA support J9E2 RP7B1A INT_PIRQC# 18,21,24 +V12S_PCI Default: 1-2 18,22 PCI_REQA# 22,44 -V12S CON3_HDR RP7F4A PCI_NOGO INT_PIRQE# 18,21,22 R7B2 0.01_1% +V3.3PCISLT3 NO_STUFF_0 +V3.3S_PCI CON3_HDR 15,18,19,20,27,30,32,35,37,38,39,43,44 +V3.3 +V5PCISLT3 RP7B1B INT_PIRQB# 15,18,21,24 +V5PCISLT3 PCI_RSV1...
Page 301 Qbuffers used for isolation during suspend 8,15,16,17,18,20,23,25,27,34,35,39,40,44,47 +V5S R9D3 as well as 5V->3.3V translation DOCK_QDEN# 25 U9D2 +V5S_QSPWR 100K 18,22,23 PCI_AD[31:0] PCI_AD22 DOCK_AD22 PCI_AD23 DOCK_AD23 C9C1 C9P1 PCI_AD26 DOCK_AD26 PCI_AD27 DOCK_AD27 22UF 0.1UF Q9D1 PCI_AD30 DOCK_AD30 BSS84 C9D1 PCI_AD31 DOCK_AD31 PCI_AD29 DOCK_AD29 0.1UF...
Page 302 J9E3A J9E3C DOCK_REQ4# 24 GND0 REQ# LPT_BUSY V_DC0 GND7 GND30 LPT_D5 V_DC1 PERR# LPT_D4 DOCK_SERR# 24 GND1 SERR# GND31 GND39 DOCK_AD17 GND2 GND8 AD17 ERROR# DOCK_AD16 RED_RTN STOP# DOCK_STOP# 24 AD16 LPT_D1 DOCK_RED DOCK_TRDY# 24 TRDY# GND32 LPT_D0 DOCK_AD13 DOCK_VSYNC VSYNC GND9 AD13...
Page 303 R4Y2 18,22,23,24,31,32,34,37 BUF_PCI_RST# PRIMARY HDD CONN J4J2 IDE_PDD[15:0] IDE_PDD[15:0] IDE_PDD7 IDE_PDD8 IDE_PDD6 IDE_PDD9 IDE_PDD5 IDE_PDD10 IDE_PDD4 IDE_PDD11 IDE_PDD3 IDE_PDD12 IDE_PDD2 IDE_PDD13 IDE_PDD1 IDE_PDD14 5,6,8,9,11,16,18,20,21,23,31,33,34,35,36,38,39,40,41,44,48 +V3.3S RP2J1C IDE_PDD0 IDE_PDD15 IDE_PDDREQ 4.7K IDE_PDIOW# R2J2 IDE_PDIOR# IDE_PD_CSEL IDE_PIORDY IDE_PDDACK# 18,21,37 INT_IRQ14 IDE_PDA1 IDE_PATADET 19,37 IDE_PDA0 IDE_PDCS1# R4Y1...
Page 304 Secondary IDE Power 8,15,16,17,18,20,23,24,25,34,35,39,40,44,47 +V5S 8,15,16,17,18,20,23,24,25,34,35,39,40,44,47 +V5S C2H1 U3H1A 0.1UF R2H5 C2H2 34,37 IDE_SPWR_EN# U3H1E 1000PF R2H6 390K 74HC14 U2H1A U2H1B R2H1 74HC14 IDE_SPWR_EN IDE_SPWR2_D IDE_SPWR2 SI4925DY SI4925DY NO_STUFF_0 +V5S_IDE_S Note: Primary IDE Power on Turner DC/DC Module 8,15,16,17,18,20,23,24,25,34,35,39,40,44,47 +V5S V5S_IDE_PD +V12S_IDE_S R2H8...
Page 305 +V5_ALWAYS 20,21,29 R4N2 +V5_USB1 0.01_1% C4B1 5,15,19,20,21,22,23,27,29,32,36,37,38,39,44,48 +V3.3ALWAYS 0.1UF +V5_ALWAYS 20,21,29 RP5B1B RP5B1A USB_OC0# 19 R4B1 U4B2 FB4B1 50OHM FB4B2 OC1# USBPWR_CONNC 50OHM OUT1 USBPWR_CONND OUT2 EN_U16 C4A1 USB_OC1# 19 OC2# C4A2 TPS2052 C4A6 C4A5 470PF 150UF 150UF 470PF L4N1 USBC_VCC USB_PN0 USBC-...
Page 306 5,15,19,20,21,22,23,27,28,32,36,37,38,39,44,48 +V3.3ALWAYS +V5_ALWAYS 20,21,28 R6B2 R6A7 R6N2 0.01_1% USB_OC3# 19 U6B1 FB5B1 50OHM OC1# +V5_USB2 USBPWR_CONNA OUT1 USBPWR_CONNB C6A12 OUT2 EN_U2 R6B3 C5B3 C5B1 USB_OC4# 19 OC2# 0.1UF TPS2052 470PF 150UF J5A1B L5M2 USBA_VCC VCC1 USBA- USB_PN3 USBA+ PORT USB_PP3 GND10 FB5B2 50OHM 90@100MHz...
Page 307 +V3.3 15,18,19,20,23,27,32,35,37,38,39,43,44 +V3.3_LAN R6A1 0.01_1% Bulk caps should be 4.7uF or higher. Layout note: Layout note: L6A1 Place 100 Ohm resistor Transmit/Receive pairs +V3.3_L_LAN close to 82562EM need to be 50 ohms C6A5 C6A7 C6A10 C6A11 C6A3 C6A2 4.7UH C6A6 C6A4 4.7UF 4.7UF...
Page 308 5,6,8,9,11,16,18,20,21,23,26,33,34,35,36,38,39,40,41,44,48 +V3.3S +V3.3S_FWH R8H5 U8H1 0.01_1% FWH_INIT# INIT# PCI_RST#_D R8W2 18,22,23,24,26,32,34,37 BUF_PCI_RST# RST# VCC2 C8W2 C8G4 C8W1 VCC1 0.1UF 10UF 0.1UF CLK_FWHPCI VCCA FGPIO4 R8W1 FGPI4 FGPIO3 R8W7 TBL# R8W8 FGPI3 TBL# FWH_TBL# 19,37 R8W3 FGPIO2 R8W6 FGPI2 FWH_WP# 19,37 FGPIO1 R8W4 FGPI1...
Page 309 5,15,19,20,21,22,23,27,28,29,36,37,38,39,44,48 +V3.3ALWAYS +V3.3ALWAYS_KBC J8A2 R9A1 Enable 1-2 (Default) Disable 0.01_1% C9A1 +V3.3ALWAYS_KBC C9N2 C9N3 C9N4 C9N1 Decode KBC Addresses J9A1 0.1UF 0.1UF 0.1UF 0.1UF Y9B1 22UF Enable 60h & 64h No Shunt (Default) Disable Shunt R8B3 R8B1 R8A3 10MHZ C9B2 C9B1 Boot Mode Programming Straps 18PF...
Page 310 KSC SUSPEND TIMER +V3.3ALWAYS_KBC +V3.3ALWAYS_KBC +V3.3ALWAYS_SMCRST R7A1 +V3.3ALWAYS_KBC C8A5 R8A4 SMC_INIT_CLK3 SMC_INIT_CLK1 SMC_INIT_CLK2 SMC_INITCLK 32 0.1UF U7A2 U7A4B U7A4C C8B1 U7A4D 74HC04 74HC04 74HC04 R7A2 Q8B1 4.7uF SMC_RST#_D SMC_RST BSS138 RST# SMC_INIT_CLK4 4.7K U7A4A 74HC04 R8B2 MAX809 J8A1 100K NMI Jumper: Shunt J8A1 Q8A1 for KSC Hardware or BSS138...
Page 311 BUF_PCI_RST# 18,22,23,24,26,31,32,37 +V5S 8,15,16,17,18,20,23,24,25,27,35,39,40,44,47 PPT_PNF# 35 J9G2 SIO_RST# J9G2 +V3.3S_SIO Enable 1-2 (Default) Disable CON3_HDR +V3.3S_SIO RP8G1A CR7G1 BAR43 U8F1 +V5S_DIODE 19,31,32,33,37 LPC_AD0 LAD0 VDD1 19,31,32,33,37 LPC_AD1 LAD1 VDD2 19,31,32,33,37 LPC_AD2 LAD2 VDD3 19,31,32,33,37 LPC_AD3 LAD3 VDD4 CLK_SIOPCI LCLK VSS5 SIO_DRQ#0 LDRQ# VSS6...
Page 312 PARALLEL PORT 60OHM@100MHZ 8,15,16,17,18,20,23,24,25,27,34,39,40,44,47 +V5S FB2A2C PPT_L_PNF# PPT_PNF# FB2A2A PPT_L_SLCT PPT_SLCT J2A1A 60OHM@100MHZ FB2A2B PPT_L_PE FLOPPY CONNECTOR PPT_PE FB2A2D PPT_L_BUSY/WAIT# PPT_BUSY/WAIT# FB2A1A PPT_L_ACK# PPT_ACK# J4H1 FB2A1B PPT_L_PD7 PPT_PD7 FLP_DENSEL# 34 FLP_DRATE0 34 FLP_INDEX# 34 PPT_L_PD6 FLP_MTR0# 34 60OHM@100MHZ PPT_L_PD5 FLP_DR0# 34 FB2A1C PPT_PD6 FB2A1D...
Page 313 +V5_PS2 KBC_SCANOUT[15:0] 32 CBTD has integrated diode for 5V to 3.3V voltage translation J9D1 C8A6 0.1UF KBC_SCANOUT0 KBC_SCANOUT1 KBC_SCANOUT2 KBC_SCANOUT3 KBC_SCANOUT4 KBC_SCANOUT5 U8A3 KBC_SCANOUT6 KBC_SCANOUT7 KBC_GP_DATA KBC_SCANOUT8 KBC_SCANOUT9 KBC_GP_CLK KBC_SCANOUT10 KBC_SCANOUT11 GP_DATA KBC_MOUSE_DATA KBC_SCANOUT12 KBC_SCANOUT13 GP_CLK KBC_MOUSE_CLK KBC_SCANOUT14 KBC_SCANOUT15 MOUSE_DATA KBC_KB_DATA MOUSE_CLK KBD_DATA...
Page 314 LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD J3H2 15,17,23,27,38,44 +V12S H_INIT# 3,18 4,18 H_PWRGD LPC Debug Slot +V3.3_LPCSLOT 20,21, 18,21 SM_INTRUDER# H_INTR 3,18 +V3.3_LPCSLOT 19,21,35 PM_RI# BUF_PCI_RST# 18,22,23,24,26,31,32,34 15,17,23,27,38,44 +V12S R4169_D 3,7,18 H_DPSLP# R3H3 18,21 SMB_ALERT# H_STPCLK# 3,18 J8F1 3,18 H_NMI...
Page 315 Processor Fan Header Test Caps 15,17,23,27,37,44 +V12S TP_220pf1 TP_220pf2 C8J7 220PF TP_330pf1 TP_330pf2 C9J4 J1E1 330PF CON3_HDR TP_0.1uf1 TP_0.1uf2 Test Caps backside C8J6 0.1UF TP_BS_100pf1 TP_BS_100pf2 TP_0.082uf1 TP_0.082uf2 C8J4 C9Y2 100pF 0.082uF TP_BS_0.01uf1 TP_BS_0.01uf2 TP_0.47uf1 TP_0.47uf2 C9Y5 0.01UF C8J5 0.47uF TP_BS_0.1uf1 TP_BS_0.1uf2 TP_0.01uf1...
Page 316 5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48 +V3.3ALWAYS Step 1 - Power OK Step 2 - VR ON C7A2 0.1UF 5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48 +V3.3S C7A4 0.1UF U7A3 U7A6 PWR_PWROK MAIN_PWROK C5B10 R5N9 C5C1 74AHC1G08 V1.5_PWRGD PM_PWROK 19,21,25,32,37 MAIN2_PWROK 2.2k 74AHC1G08 0.1UF 0.1UF U5C1 5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48 +V3.3ALWAYS U5B4 INTERPOSER_PRES# C7B2 0.1UF ON_BOARD_VR_ON 40 74AHC1G08...
Page 317 CORE_VSSSENSE THERMAL_SENSOR_VCC CORE_VCCSENSE CORE_VCCSENSE C3N1 C3N2 2.2uF 0.1uF Mobile Intel Pentium 4 Processor VID table Jumper Settings Jumper Settings 0 = LOW, 1 = HIGH 0 = LOW, 1 = HIGH +VCC_IMVP See page 39 for info. +VCC_IMVP See page 39 for info.
Page 318 Processor Decoupling 3,4,5,9,10,18,20,40,47,48 +VCC_IMVP Do Not Stuff C3P1 C3P3 C3P4 C3P2 C3P5 C2P2 C2P1 C2P3 NO_STUFF_680uF NO_STUFF_680uF NO_STUFF_680uF NO_STUFF_680uF NO_STUFF_680uF NO_STUFF_680uF NO_STUFF_680uF NO_STUFF_680uF C3C9 C3D1 C3D2 C3C10 C3C11 C3D3 C3C12 C2D2 C2C5 C2D1 C2P4 C2R2 C3P7 C3R3 C3P6 C3R2 C3P8 C3R1 C3R5 C2R7...
Page 319 44,47 1.5V_EV +V1.5S_GMCH 9,47 1.5V_EV +V1.5S_GMCH 852GME/PM VR CONTROLLER 32,37,39,40 VR_ON GMCH_VCORE_PWRGD 39,40 VR_ON GMCH_VCORE_PWRGD Title GMCH VR and VCCP Size Project: Document Number Date: Friday, May 21, 2004 Sheet...
Page 320 20,21,22,23,27,36,37,44 BOOT_1 C3G9 C3G7 C3G8 C3G10 U3G1 0.022uF VIN0 150uF 150uF 0.1UF VIN1 VIN2 9,11,12 +V2.5 VIN3 TPS54610 Single point VIN4 sense VSENSE_1 VSENSE L4G1 near load C3G5 COMP_1 PH_1 NC/Comp 47pF 4.7uH C4F1 C3V2 R3V4 PWRGD COMP_1_D 0.1UF BOOT 25.5k_1% 5600pF R3U4...
Page 321 22,23 -V12S HDM Connector Assembly (base board) HDM conn. is a modulized conn. design in 2 parts. 3 pin power C8A2 recepticle and a 72 pin recepticle. The 2 parts will be arranged as J1B1 22UF shown on this schematic page. 15,16,21 +VDC 15,17,23,27,37,38...
Page 322 Power On Sequence PCI_RST# DC/DC +VDC ICH4 +V1.5S PM_SLP_S4# +V3.3 PM_SLP_S3# PG 19 GMCH +V3.3S PG 7 +V5S POWER PS_ON_SW# PG 44 PWR_PWROK +V12S U7A3 MAIN_PWROK -V12S PM_PWROK U7A6 PG 39 MAIN2_PWROK PG 44 PG 39 U7B1 +V3A PG 39 PG 41 +V1.5A H_VIDPWRGD...
Page 323 PS_ON_SW# Reset Map PG 44 DC/DC SMC_SHUTDOWN Turner PCI_RST# BUF_PCI_RST# SLOTS PWR_PWROK PG 44 U7A3 ICH4 PM_PWROK PG22 MASTER_RESET# PG 39 PG 18 PG 40 Q9B3 PCI_GATED_RST# Core VR PG32 SLOT PG 39 PG 37 DOCKING PG 22 SLOT PG 5 PG 15 U7A4 PG 33...

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Intel 852GME Design Manual

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