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6.1.4.2.
Intel 855PM Chipset High Density Memory Support
The 855PM chipset architecture supports 2-GB of system memory. This memory capacity can be
achieved using "high-density" memory devices of various package types. Intel has done only limited
simulation and bench testing on these high-density SO-DIMM memory modules and has not seen any
functional or analog inspection failures using existing layout guidelines. Due to a lack of JEDEC
standard for high density memory; however, Intel has not done complete simulation nor validation with
all the available package configurations. Customers are strongly encouraged to perform complete
validation on their platforms based on the particular high-density memory package of their choice.
6.1.5.
Feedback – RCVENOUT#, RCVENIN#
The Intel 855PM MCH provides a feedback signal called "receive enable" (RCVEN#), which is used to
gate the strobe inputs for read data. There are two pins on the MCH to facilitate the use of RCVEN#.
The RCVENOUT# pin is an output of the MCH and the RCVENIN# pin is an input to the MCH.
RCVENOUT# must connect directly to RCVENIN#.
The diagrams and table below depict the recommended topology and layout routing guidelines for the
DDR-SDRAM feedback signal . The RCVEN# signal must be routed on the same layer as the
system memory clocks . The RCVEN# routing starting from MCH is as follows. RCVEN# should
transition immediately from the same external signal layer as MCH to the same internal signal layer as
memory clocks under the MCH, routed referenced to ground for the entire length. RCVEN# should then
transition from the internal signal layer back to the same external layer as MCH and connect the
RCVENIN# of MCH. External trace lengths should be minimized. All internal (segment L2) and
external layer signal routing (segments L1 and L3) should be ground referenced to keep the path of the
return current continuous.
Figure 89. DDR Feedback (RCVEN#) Routing Topology
Intel 855PM MCH
MCH
Die
®
Intel
855PM Chipset Platform Design Guide
MCH Pkg Route
L1
P
System Memory Design Guidelines (DDR-SDRAM)
L2
L3
Intel 855PM MCH
MCH Pkg Route
MCH
P
Die
155
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