Processor Decoupling Recommendations; Transient Response - Intel 855PM Design Manual

Platform Power Requirements
the traces going to the top MOSFETs Gates and most especially the bottom MOSFETs gates are the
same length.
Use the bulk capacitors and use multiple layer traces with heavy copper to keep the parasitic
resistance low. Use a minimum of three vias per connection on each bulk capacitor.
Place the top MOSFET drains as close to the VDC-input capacitors as possible.
The sense resistor has to be wide enough to carry the full load current. A minimum of 1 via per
Amp to the Vcc plane should be used. Use more if space permits.
Use solid 2-oz. copper fill under Drain and Source connections of the Top and Bottom MOSFETs.
The voltage regulator is usually left to the last moment. Often the allocated area is too small, a
narrow strip and the location poor. These factors combine so that the design flow, described above
usually cannot be followed.
General Rule: Copper Fill is Good. Fill the PCB with metal. There should be no large areas of the
board without metal. Widen the Grounds, Vcc and other power rails to fill any blank spots. Large
metal fill areas allow the voltage regulator to improve its heat radiation thus run cooler. Large
copper fill areas have other benefits too, including reducing stray resistance and inductance,
capturing and dissipating RF energy by allowing eddy currents to flow.
5.9.

Processor Decoupling Recommendations

Intel recommends proper design and layout of the system board bulk and high frequency decoupling
capacitor solution to meet the transient tolerance at the processor package balls. To meet the transient
response of the processor, it is necessary to properly place bulk and high frequency capacitors close to
the processor power and ground pins.
5.9.1.

Transient Response

The inductance of the motherboard power planes slows the voltage regulator's ability to respond quickly
to a current transient. Decoupling a power plane can be partitioned into several independent parts. The
closer to the load the capacitor is placed, the more stray inductance is bypassed. By bypassing the
inductance of leads, power planes, etc., less capacitance is required. However, areas closer to the load
have less room for capacitor placement and therefore, tradeoffs must be made.
The processor causes very large switching transients. These sharp surges of current occur at the
transition between low power states and the normal operating states. The system designer must provide
adequate high frequency decoupling to manage the highest frequency components of the current
transients. Larger bulk storage capacitors supply current during longer lasting changes in current
demand.
All of this power bypassing is required due to the relatively slow speed at which a DC-to-DC converter
can respond. A typical voltage converter has a reaction time on the order of 1 to 100 s while the
processor's current steps can be at shorter than 1 ns. High Frequency decoupling is typically done with
ceramic capacitors with a very low ESR. Because of their low ESR, these capacitors can act very
quickly to supply current at the beginning of a transient event. However, because the ceramic capacitors
are small, i.e. they can only store a small amount of charge, thus Bulk capacitors are needed too. Bulk
capacitors are typically polarized with high capacitance values and unfortunately higher ESLs and
ESRs. The higher ESL and ESR of the Bulk capacitor limit how quickly it can respond to a transient
event. The Bulk and high frequency capacitors working together can supply the charge needed to stay
in regulator before the regulator can react during a transient.
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Intel 855PM Chipset Platform Design Guide
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