Intel 855PM Design Manual page 369

5
17,18,19,20,24,34,41 +V5
BOOT_1
C271 C272 C274
150uF 150uF 0.1UF
VSENSE_1
COMP_1
C263
47pF
D C473
COMP_1_D
R429 1 2
25.5k_1%
5600pF
RT_1
R423
NO_STUFF_10K_1%
SS/ENA_1
J55
R199 C250
NO_STUFF_10K
CON3_HDR 0.01UF
V2.5_DDR_D R227
5.49k_1%
R426
10K_1%
VSENSE_1_D
R427 1 2
221_1%
C472
8200pF
R428
5.49k_1%
GND_DDR
R226 0
C
7,9,15,17,20,24,27,29,32,34,36,41 +V3.3
R23
10K
17,18,19,20,24,34,41 +V5
REFIN_2
C294 C295 C299
R489 U45
150uF 150uF 0.1UF 24
VIN0
23
VIN1
22
VIN2
NO_STUFF_0
21
VIN3
20 TPS54672
B VIN4
VSENSE_2
2
VSENSE
C292 COMP_2
3
NC/Comp
220PF
4
STATUS
C494
COMP_2_D BOOT_2
R487 5
BOOT
4.99k_1%
RT_2
0.082uF 28
RT
FSEL
27
ENA
26
REFIN
25
VBAIS
R263 100K
Note for layout: This part has
special pad on it's underside
C291
0.1UF
R476
3.92k_1%
C298
C491
R474 VSENSE_2_D 0.022uF
1 2
267_1%
8200pF
R484
NO_STUFF_4.99k_1%
Vtt Sense
A
5
4
C273
U34 0.022uF
24 6
VIN0 PH0
23 7
VIN1 PH1
22 8
VIN2 PH2
21 9
VIN3 PH3
20 TPS54610 10
VIN4 PH4
11
PH5
2 12
VSENSE PH6 L8
13
PH7
3 14 PH_1 1 2
NC/Comp PH8
4.7uH
4
PWRGD
5
BOOT
28 1
RT AGND
27 19
FSEL PGND0
18
PGND1
26 17
SS/ENA PGND2
16
PGND3
25 15
VBAIS PGND4
Note for layout: This part has
special pad on it's underside
C249
0.1UF
7,8 +V2.5_MCH
VR divider resistors
should be 0.1% tolerant
DDR_VR_PWRGD 36
R480
10K_1%
6
PH0
7
PH1
8
PH2
9
PH3
10
PH4
11
PH5
12
PH6 L9
13
PH7
PH_2
14 1 2
PH8
4.7uH
1
AGND
19
PGND0
18
PGND1
17
PGND2
16
PGND3
15
PGND4
Vtt Sense
DDR VR DDR VR DDR VR DDR VR
4
3
10,13 +V2.5_DDR
Single point
sense
near load
13 +V2.5
C248
0.1UF
R200 0.01_1%
Do Not Stuff
J54
1
R236
R466
10K_1%
R232 NO_STUFF_0
J56 C277
1 2
C488 NO_STUFF_0.01UF
0.01UF Do Not Stuff
Vtt Sense
+VDDR
R274
0.01_1%
14,16,22,29,34,41 PM_SLP_S3#
17,41 DC_SLP_S5#
3
2
7,8 +V2.5_MCH
17,18,19,20,24,34,41
17,18,19,20,24,34,41 +V5
VDD+
7,8 +V2.5_MCH
2 8
-
TLV2463
0 OPAMP1_P
7
+
J58
1
C286
2
3
NO_STUFF_0.01UF
NO_STUFF_CON3_HDR
7,8 +V2.5_MCH
17,18,19,20,24,34,41 +V5
J57
1
2
3
NO_STUFF_CON3_HDR
R457
10
VDD+
NO_STUFF_10K
2 U40A
-
TLV2463
1
OPAMP2_EN
5
3
+
GND
4
Single point
sense
near load
6,12,13,42 +V1.25S
C304 C330 C309 C296 C303
150uF 150uF 150uF 150uF 0.1UF
R258 0 FSEL
R475 NO_STUFF_0
2
1
+V5
R459
C280 10K
0.1UF
10
U40B
9
SM_VREF_DIMM 10
6 OPAMP1_EN
R456
GND NO_STUFF_10K
4
Note:
DO NOT STUFF R223
if both OP-AMPS
are enabled
R223 0
J53
1 2
Do Not Stuff
R458
10K
SM_VREF_MCH 6
Title
DDR_VR
Size Project: Document Number Rev
C 855PM Platform
Date: Monday, February 24, 2003 Sheet 40 of 47
1
D
C
B
A