Intel 855PM Design Manual page 46

FSB Design Guidelines
Figure 12 illustrates the processor socket vicinity escape routing of the source synchronous FSB signals
and their successful coexistence with robust power delivery. All source synchronous signals are
connected with minimum length dog bones from the BGA lands of the socket on the primary side layer
into internal layers Layer 3 and Layer 6. In Figure 11, note the changing orientation of the dog bone
"dipoles" as they rotate around the sides of the pin field to guarantee smooth escape routing on Layer 3
and Layer 6.
In addition to signal routing on the primary side, Layer 3 and Layer 6 are also used to feed the core
power delivery into the areas free of signals routing. VCCA (1.8 V) starts from the MCH in Figure 11
and is routed on Layer 3 and is connected with a cluster of vias to a VCCA flood on the primary side
layer. This feeds the primary side "U shape" on the three sides of the processor socket that feeds the
VCCA[3:0] pins. To minimize loop inductance of the VCCA (1.8 V) vias, they are accompanied by two
GND stitching vias.
Figure 13 shows a global view of FSB source synchronous signal routing and its coexistence with a
robust power delivery layout solution. Source synchronous signals are serpentine length matched on
Layer 3 and Layer 6 in the area in between the processor and Intel 855PM MCH packages per the
procedure described in Section 4.1.3.5. Also, the source synchronous address signals route around the
thermal backing plate hole and utilize the space on Layer 3 and Layer 6 in the socket vicinity to perform
trace length equalization.
Since GTLREF generation and the COMP[3:0] resistor connections minimize via use, there is minimal
interaction between these vias with the routing of the source synchronous signals. Refer to Section 4.1.7,
Figure 29, Figure 31, and Section 4.1.8.1 for further details.
Also the complete corridor flood routing of VCCA from the MCH can be seen on Figure 13 starting on
Layer 3 and then transitioning to the primary side of the motherboard with the cluster of vias next to the
processor socket. Figure 13 also illustrates why the 100-MHz clocks that are routed on Layer 3 can not
get to the processor pins on either Layer 3 nor Layer 6. Thus, the two clocks transition to the secondary
side of the motherboard (not shown in Figure 13) to obtain the shortest vertical distance to the
processor's BCLK[1:0] pins and the ITP_CLK[1:0] pins of the ITP700FLEX debug port. See Section
4.3.1 for further details.
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Intel 855PM Chipset Platform Design Guide
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