Intel 855PM Design Manual page 11

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Figures
Figure 1. Basic System Block Diagram ................................................................................... 24
Figure 2. Recommended Board Stack-Up Dimensions .......................................................... 30
Figure 3. Trace Spacing vs. Trace to Reference Plane Example ........................................... 34
Figure 4. Trace Spacing vs. Trace Width Example................................................................. 34
Figure 5. Recommended Stack-up Capacitive Coupling Model ............................................. 35
Figure 6. Common Clock Signals Example - Intel 855PM MCH Escape Routing ................. 39
Figure 7. Common Clock Signals Example - Processor Escape Routing.............................. 39
Figure 8. Common Clock Signals Example - Processor to Intel 855PM MCH
Layer 6 Routing........................................................................................................ 40
Figure 9. Layer 6 FSB Source Synchronous Signals GND Referencing
to Layer 5 and Layer 7 Ground Planes.................................................................... 42
Figure 10. Layer 3 FSB Source Synchronous Signals GND Referencing
to Layer 2 and Layer 4 Ground Planes.................................................................... 42
Figure 11. Intel 855PM MCH Source Synchronous Signals Recommended Escape Routing
Example ................................................................................................................... 47
Figure 12. Processor Source Synchronous Signals Recommended Escape Routing
Example ................................................................................................................... 48
Figure 13. Processor to Intel 855PM MCH Source Synchronous Signals Routing Example . 49
Figure 14. Reference Trace Length Selection ........................................................................ 50
Figure 15. Trace Length Equalization Procedures with Allegro*............................................. 51
Figure 16. Routing Illustration for Topology 1A ....................................................................... 52
Figure 17. Routing Illustration for Topology 1B ....................................................................... 53
Figure 18. Routing Illustration for Topology 1C....................................................................... 54
Figure 19. Routing Illustration for Topology 2A ....................................................................... 55
Figure 20. Routing Illustration for Topology 2B ....................................................................... 56
Figure 21. DPSLP# Layout Routing Example ......................................................................... 57
Figure 22. Routing Illustration for Topology 2C....................................................................... 58
Figure 23. Routing Illustration for Topology 3 ......................................................................... 59
Figure 24. Voltage Translation Circuit ..................................................................................... 60
Figure 25. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector .. 61
Figure 26. Processor RESET# Signal Routing Topology With ITP700FLEX Connector........ 61
Figure 27. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port........ 62
Figure 28. Processor and Intel 855PM MCH Host Clock Layout Routing Example ............... 64
Figure 29. Processor GTLREF Voltage Divider Network ........................................................ 65
Figure 30. Processor GTLREF Motherboard Layout .............................................................. 66
Figure 31. Intel 855PM MCH HVREF[4:0] Reference Voltage Generation Circuit ................. 67
Figure 32. Intel 855PM MCH HVREF[4:0] Motherboard Layout ............................................. 68
Figure 33. Processor COMP[3:0] Resistor Layout .................................................................. 70
Figure 34. Processor COMP[1:0] Resistor Alternative Primary Side Layout .......................... 70
Figure 35. Processor COMP[2] and COMP[0] 18-Mil Wide Dog Bones and Traces .............. 71
Figure 36. Intel 855PM MCH HRCOMP[1:0] Resistor Layout................................................. 72
Figure 37. Intel 855PM MCH HSWNG[1:0] Reference Voltage Generation Circuit................ 72
Figure 38. Intel 855PM MCH HSWNG[1:0] Layout ................................................................. 73
Figure 39. Processor Strapping Resistor Layout .................................................................... 74
Figure 40. V
Figure 41. ITP700FLEX Debug Port Signals........................................................................... 79
Figure 42. ITP_CLK to ITP700FLEX Connector Layout Example .......................................... 84
Figure 43. ITP700FLEX Signals Layout Example ................................................................... 85
Figure 44. ITP_CLK to CPU ITP Interposer Layout Example ................................................. 87
Figure 45. Intel 855PM MCH 1.8 V V
Figure 46. Processor 1.8 V VCCA[3:0] Recommended Power Delivery and Decoupling ...... 94
®
Intel 855PM Chipset Platform Design Guide
/V Routing Example....................................................................... 75
CCSENSE SSSENSE
CCGA
and V Recommended Power Delivery ........... 92
CCHA
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