Routing Guidelines; General Routing Guidelines - Intel 80331 Design Manual

I/o processor
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Routing Guidelines

This chapter provides some basic routing guidelines for layout and design of a printed circuit board
using 80331. The high-speed clocking required when designing with the 80331 requires special
attention to signal integrity. In fact, it is highly recommended that the board design be simulated to
determine optimum layout for signal integrity. The information in this chapter provides guidelines
to aid the designer with board layout. Several factors influence the signal integrity of a 80331
design. These factors include:
Power distribution
Minimizing crosstalk
Decoupling
Layout considerations when routing the DDR memory, DDR II memory, and PCI-X bus
interfaces
4.1

General Routing Guidelines

This section details general routing guidelines for designing with 80331. The order in which
signals are routed varies from designer to designer. Some designers prefer to route all clock signals
first, while others prefer to route all high-speed bus signals first. Either order can be used, provided
the guidelines listed here are followed.
Intel® 80331 I/O Processor Design Guide
Routing Guidelines
4
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