Clock Signal Length Matching Requirements - Intel 855PM Design Manual

R
6.1.4.1.

Clock Signal Length Matching Requirements

The Intel 855PM MCH provides three differential clock pair signals for each SO-DIMM. A differential
clock pair is made up of a SCK signal and its complement signal SCK#.
The differential pairs for one SO-DIMM are:
The differential pairs for the second SO-DIMM are:
The differential clock pairs' motherboard routing must be matched to ± 25 mils. Each SCK to SCK# pair
motherboard routing must be matched to ± 10 mils. Figure 86 and Figure 87 depict the length matching
requirement between SCK/SCK# and clock pairs, respectively.
For information covering the data and data strobe to clock length matching requirements reference
Section 6.1.1.2, for information covering the control signal to clock length matching requirements
reference Section 6.1.2.1, and for information covering the command signal to clock length matching
requirements reference Section 6.1.3.1.2 for Topology 1 and Section 6.1.3.2.2 for Topology 2. Refer
Section 6.1.5.1 for package trace length data.
®
Intel 855PM Chipset Platform Design Guide
SCK[0] / SCK#[0]
SCK[1] / SCK#[1]
SCK[2] / SCK#[2]
SCK[3] / SCK#[3]
SCK[4] / SCK#[4]
SCK[5] / SCK#[5]
System Memory Design Guidelines (DDR-SDRAM)
151