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7.
AGP Port Design Guidelines
For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the latest
AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This
design guide focuses only on specific Intel 855PM chipset platform recommendations.
7.1.
AGP Interface
The AGP Interface Specification Revision 2.0 enhances the functionality of the original AGP Interface
Specification (revision 1.0) by allowing 4X data transfers (4 data samples per clock) and 1.5-volt
operation. In addition to these major enhancements, additional performance enhancement and
clarifications, such as fast write capability, are included in Revision 2.0 of the AGP Interface
Specification.
The 4X operation of the AGP interface provides for "quad-sampling" of the AGP AD (Address/Data)
and SBA (Side-band Addressing) buses. That is, the data is sampled four times during each 66-MHz
AGP clock. This means that each data cycle is ¼ of a 15 ns period (66-MHz clock) or 3.75 ns. It is
important to realize that 3.75 ns is the data cycle time, not the clock cycle time. During 2X operation,
the data is sampled twice during a 66-MHz clock cycle. Therefore, the data cycle time is 7.5 ns.
In order to allow for these high-speed data transfers, the 2X mode of AGP operation uses source
synchronous data strobing. During 4X operation, the AGP interface uses differential source synchronous
data strobing. However, differential source synchronous data strobing is not strictly required by the AGP
specification.
With data cycle times as small as 3.75 ns, and setup/hold times of 1 ns, propagation delay mismatch is
critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on
the data lines will cause the settling time to be large. If the mismatch between a data line and the
associated strobe is too great, or there is noise on the interface, incorrect data will be sampled.
The low-voltage operation on AGP (1.5 V) requires even more noise immunity. For example, during
1.5-V operation, V
issues.
A single AGP controller is supported by the Intel 855PM MCH AGP interface. LOCK# and
SERR#/PERR# are not supported. The AGP buffers operate in only one mode:
AGP 4X, 2X and 1X operate at 1.5 V only.
AGP semantic cycles to DRAM are not snooped on the host bus.
The MCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either
the PIPE# or the SBA[7:0] mechanism must be selected during system initialization.
The AGP interface is clocked from the 66-MHz clock input to the MCH, 66IN. The AGP interface is
synchronous to the host and system memory interfaces with a clock ratio of 2:3 (66 MHz: 100 MHz)
and to the hub interface with a clock ratio of 1:1 (66 MHz: 66 MHz).
®
Intel
855PM Chipset Platform Design Guide
is 570 mV. Without proper isolation, crosstalk could create signal integrity
il max
AGP Port Design Guidelines
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