Holtek HT32F52220 User Manual page 8

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Register Map ..................................................................................................................... 239
Register Descriptions ......................................................................................................... 239
BFTM Control Register - BFTMCR .............................................................................................. 239
BFTM Status Register - BFTMSR ................................................................................................ 240
BFTM Counter Register - BFTMCNTR ........................................................................................ 241
BFTM Compare Value Register - BFTMCMPR ........................................................................... 241
15 Single-Channel Timer (SCTM) ......................................................................... 242
Introduction ........................................................................................................................ 242
Features ............................................................................................................................. 243
Functional Descriptions ..................................................................................................... 243
Counter Mode ............................................................................................................................... 243
Clock Controller ............................................................................................................................ 244
Trigger Controller .......................................................................................................................... 245
Slave Controller ............................................................................................................................ 246
Channel Controller ........................................................................................................................ 248
Input Stage ................................................................................................................................... 249
Output Stage ................................................................................................................................. 250
Update Management .................................................................................................................... 252
Register Map ..................................................................................................................... 253
Register Descriptions ......................................................................................................... 254
Timer Counter Configuration Register - CNTCFR ....................................................................... 254
Timer Mode Configuration Register - MDCFR ............................................................................. 255
Timer Trigger Configuration Register - TRCFR ............................................................................ 256
Timer Counter Register - CTR ..................................................................................................... 257
Channel Input Configuration Register - CHICFR ......................................................................... 258
Channel Output Configuration Register - CHOCFR ................................................................... 260
Channel Control Register - CHCTR ............................................................................................. 261
Channel Polarity Configuration Register - CHPOLR .................................................................... 262
Timer Interrupt Control Register - DICTR .................................................................................... 263
Timer Event Generator Register - EVGR ..................................................................................... 264
Timer Interrupt Status Register - INTSR ...................................................................................... 265
Timer Counter Register - CNTR................................................................................................... 266
Timer Prescaler Register - PSCR ................................................................................................ 266
Timer Counter Reload Register - CRR ........................................................................................ 267
Channel Capture/Compare Register - CHCCR ........................................................................... 268
16 Watchdog Timer (WDT) .................................................................................... 269
Introduction ........................................................................................................................ 269
Features ............................................................................................................................. 269
Functional Description ....................................................................................................... 270
Register Map ..................................................................................................................... 272
Register Descriptions ......................................................................................................... 272
Watchdog Timer Control Register - WDTCR ............................................................................... 272
Rev. 1.10 8 of 366 November 09, 2018