Ahb Clock Control Register - Ahbccr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
AHB Clock Control Register – AHBCCR
This register specifies the AHB clock enable control bits.
Offset: 0x024
Reset value: 0x0000_0065
31
Type/Reset
23
Type/Reset
15
Reserved
Type/Reset
7
Reserved
Type/Reset RW
Bits Field
[17] PBEN
[16] PAEN
[11] CKREFEN
[6] APBEN
[5] BMEN
[2] SRAMEN
Rev. 1.10
30 29 28
22 21 20
Reserved
14 13 12
6 5 4
APBEN BMEN
1 RW 1
Descriptions
GPIO Port B Clock Enable
0: Port B clock is disabled
1: Port B clock is enabled
Set and reset by software
GPIO Port A Clock Enable
0: Port A clock is disabled
1: Port A clock is enabled
Set and reset by software
CK_REF Clock Enable
0: CK_REF clock is disabled
1: CK_REF clock is enabled
Set and reset by software
APB bridge Clock Enable
0: APB bridge clock is automatically disabled by hardware during Sleep mode
1: APB bridge clock is always enabled during Sleep mode
Set and reset by software. User can set the APBEN bit to 0 to reduce the power
consumption if the APB bridge is unused during the Sleep mode.
Bus Matrix Clock Enable
0: Bus Matrix clock is automatically disabled by hardware during Sleep mode
1: Bus Matrix clock is always enabled during Sleep mode
Set and reset by software. User can set the BMEN bit to 0 to reduce the power
consumption if the bus matrix is unused during the Sleep mode.
SRAM Clock Enable
0: SRAM clock is automatically disabled by hardware during Sleep mode
1: SRAM clock is always enabled during Sleep mode
Set and reset by software. User can set the SRAMEN bit to 0 to reduce the power
consumption if the SRAM is unused during the Sleep mode.
86 of 366
27 26
Reserved
19 18
PBEN
RW
11 10
CKREFEN Reserved
RW 0
3 2
Reserved SRAMEN Reserved
RW 1
25 24
17 16
PAEN
0 RW 0
9 8
1 0
FMCEN
RW 1
November 09, 2018