32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
HSE Clock Monitor
The HSE Clock Monitor main function is enabled by the HSE Clock Monitor Enable bit CKMEN
in the Global Clock Control Register, GCCR. The HSE clock monitor function should be enabled
after the HSE oscillator start-up delay and disabled when the HSE oscillator is stopped. Once the
HSE oscillator failure is detected, the HSE oscillator will automatically be disabled. The HSE clock
stuck flag CKSF in the Global Clock Interrupt Register GCIR will be set and the HSE oscillator
failure interrupt will be generated if the clock failure interrupt enable bit CKSIE in the GCIR is
set. This failure interrupt is connected to the CPU Non-Maskable Interrupt, NMI. When the HSE
oscillator failure occurs, the HSE will be turned off and the system clock will be switched to the
HSI automatically by the hardware. If the HSE is used as the clock input of the PLL circuit and the
PLL output clock is used as the system clock, the PLL circuit will also be turned off as well as the
HSE when the failure happens.
Clock Output Capability
The device has the clock output capability to allow the clocks to be output on the specific external
output pin CKOUT. The configuration registers of the corresponding GPIO port must be well
configured in the Alternate Function I/O, AFIO, section to output the selected clock signal.
There are six output clock signals to be selected via the device clock output source selection bits
CKOUTSRC in the Global Clock Configuration Register, GCFGR.
Table 17. CKOUT Clock Source
CKOUTSRC[2:0]
Rev. 1.10
000
CK_REF = CK_PLL / (CKREFPRE + 1) / 2
001
CK_AHB / 16
010
CK_SYS / 16
011
CK_HSE / 16
100
CK_HSI / 16
101
Reserved
110
CK_LSI
76 of 366
Clock Source
November 09, 2018
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