Channel 0 Asymmetric Compare Register - Ch0Acr; Channel 1 Asymmetric Compare Register - Ch1Acr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Channel 0 Asymmetric Compare Register – CH0ACR
This register specifies the timer channel 0 asymmetric compare value.
Offset: 0x0A0
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] CH0ACV
Channel 1 Asymmetric Compare Register – CH1ACR
This register specifies the timer channel 1 asymmetric compare value.
Offset: 0x0A4
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] CH1ACV
Rev. 1.10
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Channel 0 Asymmetric Compare Value
When channel 0 is configured as asymmetric PWM mode and the counter is
counting down, the value written into this register will be compared to the counter.
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Channel 1 Asymmetric Compare Value
When channel 1 is configured as asymmetric PWM mode and the counter is
counting down, the value written into this register will be compared to the counter.
234 of 366
27 26
Reserved
19 18
Reserved
11 10
CH0ACV
0 RW 0 RW 0 RW
3 2
CH0ACV
0 RW 0 RW 0 RW
27 26
Reserved
19 18
Reserved
11 10
CH1ACV
0 RW 0 RW 0 RW
3 2
CH1ACV
0 RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
November 09, 2018