Phase Locked Loop - Pll; Figure 15. Pll Block Diagram - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Phase Locked Loop – PLL
This PLL can provide 4 ~ 48 MHz clock output which is 1~12 multiples of a fundamental reference
frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital Phase Locked
Loop (PLL) which includes a reference divider, a feedback divider, a digital phase frequency
detector (PFD), a current-controlled charge pump, a built-in loop filter and a voltage-controlled
oscillator (VCO) to achieve a stable phase-locked state.
Ref. Divider
CLK
in
(NR)
= 4 ~ 16MHz
/2

Figure 15. PLL Block Diagram

The frequency of the PLL output clock can be determined by the following formula:
PLL
where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16,
NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8
Considering the duty cycle of 50%, both input and output frequencies are divided by 2. If a
given CLK frequency used as the PLL input generates a specific PLL output frequency, it is
in
recommended to load a larger value into the NF2 field to increase the PLL stability and reduce
the jitter with expense of the settling time. The output and feedback divider 2 setup values are
described in Table 15 and Table 16. All the configuration bits (S1 ~ S0, B3 ~ B0) in Table 15 and
Table 16 are defined in the PLL Configuration Register (PLLCFGR) and PLL Control Register
(PLLCR) in the section of Register Definition. Note that the VCO
range from 48 MHz to 96 MHz. If the selected configuration exceeds this range, the PLL output
frequency will not be guaranteed to match the above PLL
The PLL can be switched on or off using the PLLEN bit in the Global Clock Control Register
(GCCR). The PLLRDY flag in the Global Clock Status Register (GCSR) will indicate if the PLL
clock is stable. An interrupt can be generated if the related interrupt enable bit PLLRDYIE in the
Global Clock Interrupt Register (GCIR) is set as the PLL becomes stable.
Rev. 1.10
PD CP
Loop
Filter
Feedback Divider 2 Feedback Divider 1
(NF2) (NF1)
/4
B3~B0
NF1×NF2
= CLK ×
OUT in NR×NO1×NO2
73 of 366
VCO = 48 ~ 96 MHz
out
Output Divider 1
VCO
(NO1)
/2
4×NF2
= CLK × = CLK
in
2×2×NO2
OUT
formula.
OUT
Output Divider 2
PLL
out
(NO2)
= 4 ~ 48 MHz
S1~S0
NF2
×
in
NO2
frequency should be in the
November 09, 2018