Usart Fifo Control Register - Usrfcr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
USART FIFO Control Register – USRFCR
This register specifies the USART FIFO control and configurations including threshold level and reset function
together with the USART FIFO status.
Offset: 0x008
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset RW 0 RW
Bits Field
[27:24] RXFS
[19:16] TXFS
[7:6] RXTL
[5:4] TXTL
[1] RXR
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
6 5 4
RXTL TXTL
0 RW 0 RW
Descriptions
RX FIFO Status
The RXFS field shows the current number of data contained in the RX FIFO.
0000: RX FIFO is empty
0001: RX FIFO contains 1 data
...
1000: RX FIFO contains 8 data
Others: Reserved
TX FIFO Status
The TXFS field shows the current number of data contained in the TX FIFO.
0000: TX FIFO is empty
0001: TX FIFO contains 1 data
...
1000: TX FIFO contains 8 data
Others: Reserved
RX FIFO Threshold Level Setting
00: 1 byte
01: 2 bytes
10: 4 bytes
11: 6 bytes
The RXTL field defines the RX FIFO trigger level.
TX FIFO Threshold Level Setting
00: 0 byte
01: 2 bytes
10: 4 bytes
11: 6 bytes
The TXTL field determines the TX FIFO trigger level.
RX FIFO Reset
Setting this bit will generate a reset pulse to reset the RX FIFO which will empty the
RX FIFO. i.e., the RX FIFO pointer will be reset to 0, after a reset signal. This bit
returns to 0 automatically after the reset pulse is generated.
344 of 366
27 26
RO 0 RO 0 RO
19 18
RO 0 RO 0 RO
11 10
Reserved
3 2
Reserved
0 WO
25 24
RXFS
0 RO 0
17 16
TXFS
0 RO 0
9 8
1 0
RXR TXR
0 WO 0
November 09, 2018