32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
Master Controller
The GPTMs and MCTMs can be linked together internally for timer synchronization or chaining.
When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will
generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or
a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive
another GPTM or MCTM, if exists, which is configured in the Slave Mode.
Figure 39. Master GPTMn and Slave GPTMm/MCTMm Connection
The Master Mode Selection bits, MMSEL, in the MDCFR register are used to select the MTO
source for synchronizing another slave GPTM or MCTM if exists.
Figure 40. MTO Selection
For example, setting the MMSEL field to 0x5 is to select the CH1OREF signal as the MTO signal
to synchronize another slave GPTM or MCTM. For a more detailed description, refer to the related
MMSEL field definitions in the MDCFR register.
Rev. 1.10
GPTMn Master
MMSEL
MTO
TSE
UEVG bit
Counter enable signal
Update Event
Channel 0 Capture/Compare event
CH0OREF
CH1OREF
CH2OREF
CH3OREF
185 of 366
GPTMm/MCTMm Slave
SMSEL
ITI
TRSEL
MTO
MMSEL
November 09, 2018
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