32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
Trigger Mode
After the counter is disabled to count, the counter can resume counting when a STI rising edge
signal occurs. When an STI rising edge occurs, the counter will start to count from the current
value in the counter. Note that if the STI signal is selected to be derived from the UEVG bit
software trigger, the counter will not resume counting. When software triggering using the UEVG
bit is selected as the STI source signal, there will be no clock pulse generated which can be used to
make the counter resume counting. Note that the STI signal is only used to enable the counter to
resume counting and has no effect on controlling the counter to stop counting.
STI source signal
STI source signal
Figure 38. GPTM in Trigger Mode
Rev. 1.10
(polarity=0)
(polarity=1)
STI
Sync
CK_CNT
CNT_EN
CNTR
27
(Up-counting)
TEVIF
184 of 366
28
29
30
31
Software clearing
November 09, 2018
32
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