Figure 102. Spi Continuous Transfer Timing Diagram - Cpol = 1, Cpha = 0; Figure 103. Spi Single Byte Transfer Timing Diagram - Cpol = 1, Cpha = 1; Figure 104. Spi Continuous Transfer Timing Diagram - Cpol = 1, Cpha = 1 - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Figure 105 shows the continuous data transfer timing of this format. Note that the SEL signal must
change to an inactive level between each data frame.
SEL (SELAP=0)
SEL (SELAP=1)
SCK
MOSI/MISO
Figure 102. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
In this format, the received data is sampled on the SCK line rising edge while the transmitted data
is changed on the SCK line falling edge. In the master mode, the first bit is driven when data is
written into the SPIDR register. In the slave mode, the first bit is driven at the first SCK falling
edge. Figure 106 shows the single byte transfer timing of this format.
SEL (SELAP=0)
SEL (SELAP=1)
SCK
MOSI
MISO
Figure 103. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1
Figure 107 shows the continuous data transfer timing of this format. Note that the SEL signal must
remain active until the last data transfer has completed.
SEL (SELAP=0)
SEL (SELAP=1)
SCK
MOSI/MISO
Figure 104. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1
Rev. 1.10
Data1
½ SCK
TX[7] TX[6] TX[5]
RX[7] RX[6] RX[5]
data sampled
Data1
312 of 366
½ SCK
½ SCK
Data2
TX[4] TX[3] TX[2] TX[1]
RX[4] RX[3] RX[2] RX[1]
Data2
TX[0]
RX[0]
November 09, 2018