Holtek HT46RU75D-1 Manual

Dual slope a/d type mcu with lcd

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Features

Operating voltage:

= 4MHz: 2.2V~5.5V

SYS

= 8MHz: 3.3V~5.5V

SYS

18 bidirectional I/O lines and two ADC inputs

Single external interrupt input shared with I/O line

One 16-bit and one 18-bit programmable timer/event

counter with overflow interrupt and prescaler

LCD driver with 40´4, 41´3 or 41´2 segments

8K´16 program memory with partial lock function

160´8 data memory RAM

Four differential input channel dual slope Analog to

Digital Converter with Operational Amplifier

Watchdog Timer with regulator power supply

Buzzer output

External 32768Hz RTC oscillator

Integrated RC or crystal oscillator

General Description

The HT46RU75D-1 is an 8-bit high performance, RISC

architecture microcontroller device specifically de-

signed for A/D with LCD applications that interface di-

rectly to analog signals, such as those from sensors.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, Dual slope A/D

Rev. 1.10

Dual Slope A/D Type MCU with LCD

HT46RU75D-1

Power-down and wake-up functions reduce power

consumption

Voltage regulator (3.3V) and charge pump

Embedded voltage reference generator (1.5V)

16-level subroutine nesting

Universal Asynchronous Receiver Transmitter -

UART

Bit manipulation instruction

16-bit table read instruction

Up to 0.5ms instruction cycle with 8MHz system clock

at V

=5V

63 powerful instructions

All instructions in 1 or 2 machine cycles

Low voltage reset/detector function

100-pin QFP package

converter, LCD display, UART function, HALT and

wake-up functions, watchdog timer, as well as low cost,

provide the flexibility to suit a wide range of AD with LCD

application possibilities such as sensor signal process-

ing, scales, consumer products, subsystem controllers,

etc.

January 10, 2008

Table of Contents

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Summary of Contents for Holtek HT46RU75D-1

Page 1 100-pin QFP package · Integrated RC or crystal oscillator General Description The HT46RU75D-1 is an 8-bit high performance, RISC converter, LCD display, UART function, HALT and architecture microcontroller device specifically de- wake-up functions, watchdog timer, as well as low cost,...
Page 2: Block Diagram
HT46RU75D-1 Block Diagram Pin Assignment H T 4 6 R U 7 5 D - 1 1 0 0 Q F P - A Rev. 1.10 January 10, 2008...
Page 3: Pin Description
HT46RU75D-1 Pin Description Pin Name Options Description PA0/BZ PA1/BZ Bidirectional 8-bit input/output port. Each individual pin on this port can Wake-up be configured as a wake-up input by a configuration option. Software in- PA3/PFD Pull-high structions determine if the pin is a CMOS output or Schmitt trigger input.
Page 4: Absolute Maximum Ratings
HT46RU75D-1 Absolute Maximum Ratings -0.3V to V Supply Voltage ......V +6.0V Storage Temperature ......-50°C to 125°C -0.3V to V Input Voltage......V +0.3V Operating Temperature......-40°C to 85°C Total ..............150mA Total............-100mA Total Power Dissipation ........500mW Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device.
Page 5 HT46RU75D-1 Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions No load, system HALT, ¾ Standby Current Analog block off, LCD on STB7 =WDT OSC) 1/3 bias, V ¾ ¾ ¾ No load, system HALT, 1200 Standby Current LCD off, UART enable =4MHZ X¢TAL/RC)
Page 6 HT46RU75D-1 Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions =3.7V~5.5V ¾ ¾ ¾ Charge pump off REGDP1 Current£10mA Regulator Output Voltage Drop (Compare with No Load) =2.4V~3.6V ¾ ¾ ¾ Charge pump on REGDP2 Current£6mA Dual Slope AD, Amplifier and Band Gap ¾...
Page 7: Functional Description
HT46RU75D-1 Functional Description Execution Flow After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by 1. The system clock is derived from either a crystal or an The PC then points to the memory word containing the external RC oscillator.
Page 8 HT46RU75D-1 · Location 00CH When a control transfer takes place, an additional Location 00CH is reserved for the Timer/Event Coun- dummy cycle is required. ter 0 interrupt service program. If a timer interrupt re- sults from a Timer/Event Counter 0 overflow, and if the...
Page 9 HT46RU75D-1 start of a subroutine call or an interrupt acknowledg- ment, the contents of the program counter is pushed onto the stack. At the end of the subroutine or interrupt routine, indicated by a return instruction, RET or RETI, the contents of the program counter is restored to its previous value from the stack.
Page 10 HT46RU75D-1 Accumulator - ACC pushed onto the stack. If the contents of the status regis- ter is important, and if the subroutine is likely to corrupt The accumulator, ACC, is related to the ALU operations. the status register, the programmer should take precau- It is mapped to location 05H of the RAM and is capable tions and save it properly.
Page 11 HT46RU75D-1 low to high and high to low. Its related interrupt request The A/D converter interrupt is generated when the A/D flag, EIF0; bit 4 of INTC0, must also be set. After the in- converter interrupt request flag, ADF; bit 5 of INTC1 is terrupt is enabled, if the stack is not full and the external set.
Page 12 HT46RU75D-1 latter of the two T2 pulses if the corresponding interrupts the most cost effective clock implementation, however, are enabled. In the case of simultaneous requests, the the frequency of the oscillation may vary with VDD, tem- priorities in the following table apply. These can be perature and process variations.
Page 13 HT46RU75D-1 Watchdog Timer for analog component adjustment. The WDT oscillator ranges from 2 the exact value of which is deter- needs to be disabled/enabled using its registers, WDTC mined by a configuration option, to obtain the actual and WDTOSC, to minimise power consumption.
Page 14 HT46RU75D-1 only the PC and SP are reset to zero. There are three RTC Clock Divided Factor methods to clear the contents of the WDT, an external low level on RES, a software instruction or a ²HALT² in- struction. There are two types of software instructions;...
Page 15 HT46RU75D-1 ting bits PAC0 and PAC1 of the PAC port control regis- the configuration option has configured it as a BZ buzzer ter to zero. The PA0 data bit in the PA data register must output. also be set high to enable the buzzer outputs, if set low, Note that no matter what configuration option is chosen both pins PA0 and PA1 will remain low.
Page 16 HT46RU75D-1 Power Down Operation - HALT stimulus, the program will resume execution at the next instruction. However, if awakening from an inter- The Power-down mode is initialised by a ²HALT² instruc- rupt, two sequences may occur. If the related inter- tion and results in the following.
Page 17 HT46RU75D-1 Reset There are three ways in which a reset may occur. · RES is reset during a normal operation · RES is reset during Power-down · WDT time-out is reset during normal operation The WDT time-out during when in the Power-down mode differs from other reset conditions, as it performs a ²warm...
Page 18 HT46RU75D-1 The register states are summarised below: Reset WDT Time-out RES Reset RES Reset WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (HALT) (HALT)* xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx xxxx uuuu uuuu uuuu uuuu...
Page 19 HT46RU75D-1 Timer/Event Counter There are four registers related to Timer/Event Counter 1, TMR1HH, TMR1H, TMR1L and TMR1C. Writing to Two timer/event counters are integrated within the TMR1L and TMR1H will only put the required data into microcontroller. Timer/Event Counter 0 contains a 16-bit...
Page 20 HT46RU75D-1 Bit No. Label Function To define the prescaler stages. T0PSC2, T0PSC1, T0PSC0= 000: f 001: f T0PSC0 010: f T0PSC1 011: f T0PSC2 100: f 101: f 110: f 111: f /128 Defines the timer/event counter TMR0 pin active edge type: In the Event Counter Mode - T0M1,T0M0 = 0,1: 1:count on falling edge;...
Page 21 HT46RU75D-1 be set to 1. In the pulse width measurement mode, the structures can be reconfigured dynamically under soft- T0ON/T1ON bit is automatically cleared after the mea- ware control. To function as an input, the corresponding latch of the control register must be written with a ²1².
Page 22 HT46RU75D-1 Input/Output Ports The PA3 pin is pin-shared with the PFD signal. If the The descriptions of the PFD control signal and PFD out- PFD option is selected, the output signal in the output put frequency are listed in the following table.
Page 23 HT46RU75D-1 PC0/TX Block Diagram PC1/RX Block Diagram Rev. 1.10 January 10, 2008...
Page 24 HT46RU75D-1 Charge Pump and Voltage Regulator A charge pump and voltage regulator are integrated within the device. The charge pump can be enabled/dis- abled by the application program. The charge pump uses VDD as its input, and has the function of doubling...
Page 25 HT46RU75D-1 this bit is disabled, then the regulator will be disabled microcontroller. The dual slope module includes an Op- and the charge pump will be also be disabled to save erational Amplifier and a buffer for the amplification of power. When REGCEN = 0, the module will enter the differential signals and an Integrator and comparator for Power Down Mode ignoring the CHPEN setting.
Page 26 HT46RU75D-1 will enable the Chopper clock, with the clock frequency The PB port can be set as A/D converter inputs or as defined by the ADCD registers. The ADC module in- general purpose bi-directional lines. The PCR2:0 bits cludes the OPA, buffer, integrator and comparator, how- define the number of A/D input lines.
Page 27 HT46RU75D-1 The following descriptions are based on the fact that to the block diagram. The charge and discharge curves ADRR0=0 are illustrated by the following. C o m p a r a t o r The ²comparator² will switch the state from high to low when VC, which is the DSCC pin voltage,drops to less than 1/6 VDSO.
Page 28 HT46RU75D-1 Bit No. Label Function Dual slope block - including input OP - power on/off switch. 0: Disable Power ADPWREN 1: Power source is sourced from the regulator. Defines the ADC discharge/charge. 00: reserved ADDISCH0~ 01: charging - Integrator input is connect to the buffer output...
Page 29 HT46RU75D-1 Bit No. Label Function Unused bit, read as ²0² ¾ Select the ADC charge timer CHGTS 0: Timer/Event Counter 0 1: Timer/Event Counter 1 Select the ADC discharge timer DISTS 0: Timer/Event Counter 0 1: Timer/Event Counter 1 Select if the charge timer (note 1) will auto-start by the ADCMPO result or not. ASTEN should be enabled.
Page 30 HT46RU75D-1 LCD Driver Output pacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage can be 1/2 bias or 1/3 bias The output number of the device LCD driver can be by option. If 1/2 bias is selected, a capacitor mounted 41´2, 41´3 or 40´4 by configuration option (i.e., 1/2, 1/3...
Page 31 HT46RU75D-1 LCD Driver Output (1/4 Duty) LCD Type R Type C Type LCD Bias Type 1/2 bias 1/3 bias 1/2 bias 1/3 bias If V >V , then V connect to V If V > , then V connect to V...
Page 32 HT46RU75D-1 Low Voltage Reset/Detector Functions When the LVD function configuration option is set to the enable state, the LVD voltage option will decide the de- There is a low voltage detector, LVD, and a low voltage tecting voltage. When the LVD configuration option is r e s e t c i r c u i t , LV R , i m p l e m e n t e d w i t h i n t h e set to LVR+0.2, the actual LVD voltage depends upon...
Page 33 TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin, The HT46RU75D-1 device contain an integrated full-du- which can also be used as a general purpose I/O pin, plex asynchronous serial communications UART inter-...
Page 34 HT46RU75D-1 · USR register RXIF flag is cleared when the USR register is read The USR register is the status register for the UART, with RXIF set, followed by a read from the RXR reg- which can be read by the program to determine the ister, and if the RXR register has no data available.
Page 35 HT46RU75D-1 ¨ used. When this bit is equal to ²1² two stop bits are PERR used, if the bit is equal to ²0² then only one stop bit The PERR flag is the parity error flag. When this read only flag is ²0² it indicates that a parity error is used.
Page 36 HT46RU75D-1 · UCR2 register input pin will wake-up the device. If this bit is equal to ²0² and if the MCU is in the Power Down Mode, The UCR2 register is the second of the two UART control registers and serves several purposes. One of...
Page 37 HT46RU75D-1 ¨ TXEN By programming the BRGH bit which allows selection of the related formula and programming the required The TXEN bit is the Transmitter Enable Bit. When value in the BRG register, the required baud rate can this bit is equal to ²0² the transmitter will be disabled be setup.
Page 38 HT46RU75D-1 Baud Rates for BRGH=1 Baud Rate =8MHz =7.159MHz =4MHz =3.579545MHz K/BPS Kbaud Error Kbaud Error Kbaud Error Kbaud Error ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 1.202 0.16 1.203...
Page 39 HT46RU75D-1 ¨ Transmitting data Start Data Address Parity Stop Bits Bits Bits When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the Example of 8-bit Data Formats least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register.
Page 40 HT46RU75D-1 ¨ Transmit break Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin. If the TXBRK bit is set then break characters will be sent on the next transmission. Break character At this point the receiver will be enabled which will transmission consists of a start bit, followed by 13´...
Page 41 HT46RU75D-1 ¨ Receiver interrupt No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself The read only receive interrupt flag RXIF in the USR generates an interrupt. register is set by an edge generated by the receiver.
Page 42 HT46RU75D-1 the UCR2 register is set. The two transmitter interrupt mode is enabled, then to ensure correct operation, the conditions have their own corresponding enable bits, parity function should be disabled by resetting the par- while the two receiver interrupt conditions have a ity enable bit to zero.
Page 43 HT46RU75D-1 Options The following shows the options in the device. All options must be defined for proper device operation. Options OSC type selection. There are two types: Crystal OSC or RC OSC System clock selection: OSC or RTC clock source.
Page 44: Application Circuits
HT46RU75D-1 Application Circuits S e e r i g h t s i d e R C S y s t e m O s c i l l a t o r C r y s t a l S y s t e m...
Page 45: Instruction Set
For easier understanding of the various instruction The standard logical operations such as AND, OR, XOR codes, they have been subdivided into several func- and CPL all have their own instruction within the Holtek tional groupings. microcontroller instruction set. As with the case of most...
Page 46 In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² in- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to...
Page 47 HT46RU75D-1 Mnemonic Description Cycles Flag Affected Rotate RRA [m] Rotate Data Memory right with result in ACC None Note RR [m] Rotate Data Memory right None RRCA [m] Rotate Data Memory right through Carry with result in ACC Note RRC [m]...
Page 48: Instruction Definition
HT46RU75D-1 Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ¬ ACC + [m] + C...
Page 49 HT46RU75D-1 CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address.
Page 50 HT46RU75D-1 CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ¬ [m] Operation Affected flag(s) CPLA [m]...
Page 51 HT46RU75D-1 INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. [m] ¬ [m] + 1 Operation Affected flag(s) INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu- lator.
Page 52 HT46RU75D-1 OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²OR² x Operation Affected flag(s)
Page 53 HT46RU75D-1 RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0.
Page 54 HT46RU75D-1 SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Page 55 HT46RU75D-1 SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
Page 56 HT46RU75D-1 SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 « [m].7 ~ [m].4 Operation Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
Page 57 HT46RU75D-1 XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²XOR² [m] Operation Affected flag(s)
Page 58: Package Information
HT46RU75D-1 Package Information 100-pin QFP (14´20) Outline Dimensions Dimensions in mm Symbol Min. Nom. Max. ¾ 18.5 19.2 ¾ 13.9 14.1 ¾ 24.5 25.2 ¾ 19.9 20.1 ¾ ¾ 0.65 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾...
Page 59 Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used...

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