Global Clock Control Register - Gccr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Global Clock Control Register – GCCR
This register specifies the clock enable bits.
Offset: 0x004
Reset value: 0x0000_0803
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[17] PSRCEN
[16] CKMEN
[11] HSIEN
[10] HSEEN
Rev. 1.10
30 29 28
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Power Saving Wakeup RC Clock Enable
0: No action
1: Use Internal 8 MHz RC clock (HSI) as system clock after power down wakeup.
The software can set the PSRCEN bit high before entering the power saving mode
in order to reduce the waiting time after a wakeup. When the PSRCEN bit is set to
1, the HSI will be used as the CK_SYS clock source after waking up from the power
saving mode. This means that the instruction can be executed early before the
original clock CK_SYS source is stable since the HSI clock is provided to CPU. After
the original CK_SYS clock source is ready, the CK_SYS clock will automatically be
switched back to the original selected clock source from the HSI clock.
HSE Clock Monitor Enable
0: Disable External 4 ~ 16 MHz crystal oscillator clock monitor
1: Enable External 4 ~ 16 MHz crystal oscillator clock monitor
When the hardware detects that the HSE clock is stuck at a low or high state, the
internal hardware will switch the system clock to the internal high speed RC clock,
HSI.
Internal High Speed Oscillator Enable
0: Internal 8 MHz RC oscillator is disabled
1: Internal 8 MHz RC oscillator is enabled
Set and reset by software. This bit can not be reset if the HSI clock is used as
system clock.
External High Speed Oscillator Enable
0: External 4 ~ 16 MHz crystal oscillator is disabled
1: External 4 ~ 16 MHz crystal oscillator is enabled
Set and reset by software. This bit can not be reset if the HSE clock is used as the
system clock or the PLL input clock.
80 of 366
27 26
Reserved
19 18
PSRCEN
RW
11 10
HSIEN HSEEN PLLEN
RW 1 RW 0 RW
3 2
RW 0 RW
25 24
17 16
CKMEN
0 RW 0
9 8
HSEGAIN
0 RW 0
1 0
SW
1 RW 1
November 09, 2018