Figure 100. Spi Continuous Transfer Timing Diagram - Cpol = 0, Cpha = 1; Figure 101. Spi Single Byte Transfer Timing Diagram - Cpol = 1, Cpha = 0 - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Figure 103 shows the continuous data transfer diagram timing. Note that the SEL signal must
remain active until the last data transfer has completed.
SEL (SELAP=0)
SEL (SELAP=1)
SCK
MOSI/MISO
Figure 100. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
In this format, the received data is sampled on the SCK line falling edge while the transmitted
data is changed on the SCK line rising edge. In the master mode, the first bit is driven when data
is written into the SPIDR register. In the slave mode, the first bit is driven when the SEL signal
changes to an active level. Figure 104 shows the single byte transfer timing of this format.
SEL (SELAP=0)
SEL (SELAP=1)
SCK
MOSI
MISO
Figure 101. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0
Rev. 1.10
Data1
½ SCK
TX[7] TX[6] TX[5]
RX[7] RX[6] RX[5]
data sampled
311 of 366
Data2
TX[4] TX[3] TX[2] TX[1]
RX[4] RX[3] RX[2]
TX[0]
RX[1] RX[0]
November 09, 2018