Flash Pre-Fetch Control Register - Cfcr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Flash Pre-fetch Control Register – CFCR
This register is used to control the FMC pre-fetch module.
Offset: 0x200
Reset value: 0x0000_0011
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[4] PFBE
[2:0] WAIT
Rev. 1.10
30 29 28
22 21 20
14 13 12
6 5 4
PFBE
RW
Descriptions
Pre-fetch Buffer Enable Bit
0: Pre-fetch buffer is disabled
1: Pre-fetch buffer is enabled (default)
The pre-fetch buffer is enabled in default. When the pre-fetch buffer is disabled,
the instruction and data are directly provided by the Flash memory.
Flash Wait State Setting
The WAIT[2:0] field is used to set the HCLK wait clock during a non-sequential
address Flash access. The actual wait clock is given by (WAIT[2:0] - 1). Since
a wide access interface with a pre-fetch buffer is provided, the wait state of
sequential Flash access is very close to zero.
WAIT [2:0] Wait Status
001 0 0 MHz < HCLK ≤ 20 MHz
010 1 20 MHz < HCLK ≤ 40 MHz
Others Reserved Reserved
55 of 366
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
Reserved
1 RW 0 RW
Allowed HCLK Range
25 24
17 16
9 8
1 0
WAIT
0 RW 1
November 09, 2018