Uart Status & Interrupt Flag Register - Ursifr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Bits Field
[1] TXDEIE
[0] RXDRIE
UART Status & Interrupt Flag Register – URSIFR
This register contains the corresponding UART status.
Offset: 0x010
Reset value: 0x0000_0180
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
TXDE Reserved
Type/Reset RO 1
Bits Field
[8] TXC
[7] TXDE
Rev. 1.10
Descriptions
Transmit Data Register Empty Interrupt Enable
0: Disable interrupt
1: Enable interrupt
An interrupt is generated when the transmit data register empty interrupt is
enabled and the TXDE bit is set in the URSIFR register.
Receive Data Ready Interrupt Enable
0: Disable interrupt
1: Enable interrupt
An interrupt is generated when the receive data ready interrupt is enabled and the
RXDR bit is set in the URSIFR register.
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
RXDR BII
RO 0 WC
Descriptions
Transmit Complete
0: Either the transmit data register (TDR) or transmit shift register (TSR) is not
empty
1: Both the transmit data register (TDR) and transmit shift register (TSR) are
empty
An interrupt is generated if this bit is set to 1 and TXCIE=1 in the URIER register.
This bit is cleared by a write to the URDR register with new data.
Transmit Data Register Empty
0: Transmit data register is not empty
1: Transmit data register is empty
The TXDE bit is set by hardware when the content of the transmit data register is
transferred to the transmit shift register (TSR). An interrupt is generated if this bit
is set to 1 and TXEIE=1 in the URIER register. This bit is cleared by a write to the
URDR register with new data.
362 of 366
27 26
Reserved
19 18
Reserved
11 10
3 2
FEI PEI
0 WC 0 WC 0 WC
25 24
17 16
9 8
TXC
RO 1
1 0
OEI Reserved
0
November 09, 2018