1.5 V Power Domain; Operation Modes; Table 11. Operation Mode Definitions - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
High Speed External Oscillator
The High Speed External Oscillator, HSE, is located in the V
oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register,
GCCR. The HSE clock can then be used directly as the system clock source or be used as the PLL
input clock.
Isolation Cells
When the device resumes operation from the 1.5 V power, either by Hardware or Software, access
to the PWRCU registers in the V
these registers against possible parasitic write accesses. To resume access operations, users must
disable these isolation cells by setting the VDDISO bit to 1 in the LPCR register of the Clock
Control Unit.

1.5 V Power Domain

The main functions that include the APB interface for the V
peripherals and memories and so on are located in this power domain. Once the 1.5 V is powered
up, the POR will generate a reset sequence on 1.5 V power domain. Subsequently, to enter the
expected power saving mode, the associated control bits including the LDOOFF, DMOSON and
LDOLCM bits must be configured. Then, once a WFI or WFE instruction is executed, the device
will enter an expected power saving mode which will be discussed in the following section.

Operation Modes

Run Mode
In the Run mode, the system operates with full functions and all power domains are active. There
are two ways to reduce the power consumption in this mode. The first is to slow down the system
clock by setting the AHBPRE field in the CKCU AHBCFGR register, and the second is to turn
off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down
peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application
requirement. Reducing the system clock speed before entering the sleep mode will also help to
minimize power consumption.
Additionally, there are several power saving modes to provide maximum optimization between
device performance and power consumption.

Table 11. Operation Mode Definitions

Mode name
Run
Sleep
Deep-Sleep1~2
Power-Down
Rev. 1.10
power domain are disabled by the isolation cells which protect
DD
After system reset, CPU fetches instructions to execute.
1. CPU clock will be stopped.
2. Peripherals, Flash and SRAM clocks can be stopped by setting.
1. Stop all clocks in the 1.5 V power domain.
2. Disable HSI, HSE, and PLL.
3. Turning on the LDO low current mode or DMOS to reduce the 1.5 V power
domain current.
Shut down the 1.5 V power domain
60 of 366
power domain. The HSE crystal
DD
domain, CPU core logic, AHB/APB
DD
Hardware Action
November 09, 2018