System Architecture; Arm ® Cortex ® -M0+ Processor - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
3

System Architecture

The system architecture of devices that includes the Arm
and memory organization will be described in the following sections. The Cortex
generation processor core which offers many new features. Integrated and advanced features make
the Cortex ® -M0+ processor suitable for market products that require microcontrollers with high
performance and low power consumption. In brief, The Cortex
bus interface. All memory accesses of the Cortex
bus according to the different purposes and the target memory spaces. The memory organization
uses a Harvard architecture, pre-defined memory map and up to 4 GB of memory space, making
the system flexible and extendable.
Arm Cortex -M0+ Processor
® ®
The Cortex ® -M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,
low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb
instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
Some system peripherals listed below are also provided by Cortex
▄
Internal Bus Matrix connected with AHB-Lite Interface, Single-cycle I/O port and Debug
Accesses Port (DAP)
▄
Nested Vectored Interrupt Controller (NVIC)
▄
Optional Wakeup Interrupt Controller (WIC)
▄
Breakpoint and Watchpoint Unit
▄
Optional Memory Protection Unit (MPU)
▄
Serial Wire debug Port (SW-DP)
▄
Optional Micro Trace Buffer Interface (MTB)
The following figure shows the Cortex
to the Arm ® Cortex
Rev. 1.10
-M0+ processor block diagram. For more information, refer
®
® -M0+ Technical Reference Manual.
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® Cortex ® -M0+ processor, bus architecture
® -M0+ processor includes AHB-Lite
® -M0+ processor are executed on the AHB-Lite
® -M0+:
® -M0+ is a next
®
November 09, 2018