Holtek HT32F52220 User Manual page 360

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Bits Field
[14] BCB
[13] SPE
[12] EPE
[11] PBE
[10] NSB
[9:8] WLS
[5] URRXEN
[4] URTXEN
[2] TRSM
Rev. 1.10
Descriptions
Break Control Bit
When this bit is set to 1, the serial data output on the UART TX pin will be forced to
the Spacing State (logic 0). This bit acts only on the UART TX output pin and has no
effect on the transmitter logic.
Stick Parity Enable
0: Disable stick parity
1: Stick Parity bit is transmitted
This bit is only available when the PBE bit is set to 1. If both the PBE and SPE bits
are set to 1 and the EPE bit is cleared to 0, the transmitted parity bit will be stuck to
1. However, when the PBE and SPE bits are set to 1 and also the EPE bit is set to
1, the transmitted parity bit will be stuck to 0.
Even Parity Enable
0: Odd number of logic 1's are transmitted or checked in the data word and parity
bits
1: Even number of logic 1's are transmitted or checked in the data word and
parity bits
This bit is only available when the PBE bit is set to 1.
Parity Bit Enable
0: Parity bit is not generated (transmitted data) and checked (receive data) during
transfer
1: Parity bit is generated and checked during transfer
Note: When the WLS field is set to "10" to select the 9-bit data format, writing to the
PBE bit has no effect.
Number of "STOP bit"
0: One "STOP bit" is generated in the transmitted data
1: Two "STOP bit" is generated when 8- and 9-bit word length is selected
Word Length Select
00: 7 bits
01: 8 bits
10: 9 bits
11: Reserved
UART RX Enable
0: Disable
1: Enable
UART TX Enable
0: Disable
1: Enable
Transfer Mode Selection
This bit is used to select the data transfer protocol.
0: LSB first
1: MSB first
360 of 366 November 09, 2018