Timer Trigger Configuration Register - Trcfr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Timer Trigger Configuration Register – TRCFR
This register specifies the SCTM trigger source selection.
Offset: 0x008
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[3:0] TRSEL
Rev. 1.10
30 29 28
22 21 20
14 13 12
6 5 4
Reserved
Descriptions
Trigger Source Selection
These bits are used to select the trigger input (STI) for counter synchronizing.
0000: Software Trigger by setting the UEVG bit
0001: Filtered input of channel (TIS)
0011: Reserved
1000: Channel both edge detector (TIBED)
Others: Default 0
Note: These bits must be updated only when they are not in use, i.e. the slave mode
is disabled by setting the SMSEL field to 0x00.
256 of 366
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
TRSEL
RW 0 RW 0 RW
25 24
17 16
9 8
1 0
0 RW 0
November 09, 2018