Figure 32. Center-Aligned Counting Example - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Center-Align Counting
In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value
and then counts down to 0 alternatively. The Timer module generates an overflow event when the
counter counts to the counter-reload value in the up-counting mode and generates an underflow
event when the counter counts to 0 in the down-counting mode. The counting direction bit DIR in
the CNTCFR register is read-only and indicates the counting direction when in the center-align
mode. The counting direction is updated by hardware automatically.
Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of
whether the counter is counting up or down in the center-align counting mode.
The UEVIF bit in the INTSR register can be set to 1 when an overflow or underflow event or both
of them occur according to the CMSEL field setting in the CNTCFR register.
CK_PSC
CNT_EN
CK_CNT
CNTR
CRR
CRR Shadow Register
Counter Overflow
Counter Underflow
Update Event Flag

Figure 32. Center-aligned Counting Example

Rev. 1.10
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Write a new value
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Software clearing
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Software clearing
November 09, 2018