Page 1 A/D Flash MCU with EEPROM HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Revision: V2.50 Date: ��ne 22� 20�� ne 22� 20��...
Page 2: Table Of Contents
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Table of Contents Features ......................7 CPU Feat�res ........................� Peripheral Feat�res ........................ 8 General Description ..................9 Selection Table ....................10 Block Diagram ....................11 Pin Assignment ....................12 Pin Description ....................16 Absolute Maximum Ratings ................
Page 3 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM EEPROM Data Memory .................. 44 EEPROM Data Memory Str�ct�re ..................44 EEPROM Registers ......................44 Reading Data from the EEPROM ..................48 Writing Data to the EEPROM ....................48 Write Protection ........................48 EEPROM Interr�pt ........................
Page 4 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Timer Modules – TM ..................99 Introd�ction ........................... 99 TM Operation ........................�00 TM Clock So�rce ......................... �00 TM Interr�pts ........................�00 TM External Pins ......................... �0� TM Inp�t/O�tp�t Pin Control Registers ................�02 Programming Considerations ....................��...
Page 5 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Interrupts ...................... 202 Interr�pt Registers ....................... 202 Interr�pt Operation ......................2�6 External Interr�pt ......................... 220 Comparator Interr�pt ......................220 M�lti-f�nction Interr�pt ......................220 A/D Converter Interr�pt ....................... 22� Time Base Interr�pt ......................22�...
Page 6 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Instruction Set ....................259 Introd�ction ......................... 259 Instr�ction Timing ........................ 259 Moving and Transferring Data ..................... 259 Arithmetic Operations ......................259 Logical and Rotate Operation ..................... 260 Branches and Control Transfer ................... 260 Bit Operations ........................
Page 7: Features
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Features CPU Features • Operating Voltage: =8MHz: 2.2V~5.5V ♦ =12MHz: 2.7V~5.5V ♦ =20MHz: 4.5V~5.5V ♦ • Up to 0.2μs instruction cycle with 20MHz system clock at V • Power down and wake-up functions to reduce power consumption • Five oscillators: External Crystal -- HXT ♦ External 32.768kHz Crystal -- LXT ♦ External RC -- ERC ♦ Internal RC -- HIRC ♦ Internal 32kHz RC -- LIRC ♦ • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instructions...
Page 8: Peripheral Feat�Res
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Peripheral Features • Flash Program Memory: 1K×14~12K×16 • RAM Data Memory: 64×8~576×8 • True EEPROM Memory: 32×8~256×8 • Watchdog Timer function • Up to 50 bidirectional I/O lines • Software controlled 4-SCOM lines LCD driver with 1/2 bias • Multiple pin-shared external interrupts • Multiple Timer Module for time measure, input capture, compare match output, PWM output or single pulse output function • Serial Interfaces Module -- SIM for SPI or I • Dual Comparator functions • Dual Time-Base functions for generation of fixed time interrupt signals • Multi-channel 12-bit resolution A/D converter • Low voltage reset function • Low voltage detect function • Optional peripheral -- UART module for fully duplex asynchronous communication • Wide range of available package types...
Page 9: General Description
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM General Description The HT66FXX series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontrollers. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non- volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter and dual comparator functions. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully...
Page 10: Selection Table
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Selection Table Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O count, TM features, stack capacity and package types. The following table summarises the main features of each device. Program Data Data Ext. Timer Interface Part No. UART Stacks Package Memory Memory EEPROM Int. Module (SPI/I �0-bit CTM×� �6DIP/NSOP/SSOP HT66F20 2.2V~5.5V �k×�4 64×8 32×8 �8 �2-bit×8 √...
Page 11: Block Diagram
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Block Diagram L o w W a t c h d o g V o l t a g e T i m e r D e t e c t R e s e t...
Page 12: Pin Assignment
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Pin Assignment P A 0 / C 0 X / T P 0 _ 0 / A N 0 P A 1 / T P 1 _ 0 / A N 1 V S S & A V S S...
Page 13 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P D 2 / [ T C K 0 ] / [ S D I / S D A ] P B 5 / S C S / V R E F P D 3 / [ T C K 1 ] / [ S D O ]...
Page 14 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P A 0 / C 0 X / T P 0 _ 0 / A N 0 P A 1 / T P 1 A / A N 1 V S S & A V S S...
Page 15 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P A 0 / C 0 X / T P 0 _ 0 / A N 0 P A 1 / T P 1 A / A N 1 V S S & A V S S...
Page 16: Pin Description
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Pin Description With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Serial Port pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. The following tables only include the pins which are directly related to the MCU. The pin descriptions of the additional peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional description. HT66F20 Pin Name Function Pin-Shared Mapping PAWU PA0~PA� Port A CMOS —...
Page 17 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. HT66F30 Pin Name Function Pin-Shared Mapping PAWU PA0~PA� Port A CMOS — PAPU PB0~PB5 Port B PBPU CMOS — PC0~PC� Port C PCPU CMOS —...
Page 18 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. HT66F40 Pin Name Function Pin-Shared Mapping PAWU PA0~PA� Port A CMOS — PAPU PB0~PB� Port B PBPU CMOS — PC0~PC� Port C PCPU CMOS —...
Page 19 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Pin Name Function Pin-Shared Mapping AVDD ADC power s�pply* — — — Gro�nd** — — — AVSS ADC gro�nd** — — — Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog signal HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded...
Page 20 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Pin Name Function Pin-Shared Mapping SPI Data inp�t PRM0 — PA6 or PD2 or PB� SPI Data o�tp�t PRM0 — CMOS PA5 or PD3 or PB6 SPI Slave Select PRM0 CMOS PB5 or PD0 or PD�...
Page 21 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM HT66F60 Pin Name Function Pin-Shared Mapping PAWU PA0~PA� Port A CMOS — PAPU PB0~PB� Port B PBPU CMOS — PC0~PC� Port C PCPU CMOS — PD0~PD� Port D PDPU CMOS — PE0~PE� Port E...
Page 22: Absolute Maximum Ratings
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Pin Name Function Pin-Shared Mapping AVDD ADC power s�pply* — — — Gro�nd** — — — AVSS ADC gro�nd** — — — Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog signal HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded...
Page 23: D.c. Characteristics
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions =8MHz — Operating Voltage — =�2MHz 2.� — (HXT� ERC� HIRC) =20MHz — — 0.� �.� No load� f =4MHz� ADC off� WDT enable —...
Page 24 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions =-3.2mA 2.� — — O�tp�t High Voltage I/O Port =-�.4mA — — �00 kΩ P�ll-high Resistance for I/O Ports — �0 kΩ SCOMC� ISEL[�:0]=00 ��.5...
Page 25: A/D Converter Characteristics
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Ta=25°C -�0% +�0% kHz System Clock (LIRC) LIRC 2.2V~5.5V Ta=-40°C~85°C -50% +60% kHz Timer Inp�t Pin Freq�ency — — — — � TIMER External Reset Low P�lse Width —...
Page 26: Comparator Electrical Characteristics
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Comparator Electrical Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Comparator Operating Voltage — — — — — 3� μA Comparator Operating C�rrent — — �30 μA Comparator Inp�t Offset Voltage —...
Page 27: System Architecture
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator...
Page 28 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. F e t c h I n s t . 1 E x e c u t e I n s t . 1 M O V A , [ 1 2 H ] F e t c h I n s t .
Page 29: Stack
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P r o g r a m C o u n t e r T o p o f S t a c k...
Page 30: Flash Program Memory
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 1K×14 bits to 12K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries.
Page 31: Special Vectors
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 0000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD [m]" or "TABRDL [m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0".
Page 32 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "700H" which refers to the start address of the last page within the 2K Program Memory of the HT66F30. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "706H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the address specified by the TBLP and TBHP if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require...
Page 33: In Circ�It Programming - Icp
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. MCU Programming Pins Function Serial Data Inp�t/O�tp�t Serial Clock Device Reset Power S�pply...
Page 34: Data Memory
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into several banks, the structure of which depends upon the device chosen. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. Device Capacity Banks 0: 60H~�FH HT66F20 64×8 �: 60H~�FH 0: 60H~�FH HT66F30 96×8 �: 60H~�FH 2: 60H~�FH...
Page 35 A D R H 5 F H U n u s e d A D R H 5 F H U n u s e d HT66F20 Special Purpose Data Memory HT66F30 Special Purpose Data Memory Rev. 2.50 ��ne 22� 20��...
Page 36 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM B a n k 0 , 1 B a n k 0 B a n k 1 B a n k 0 , 1 , 2 B a n k 0 , 2...
Page 37 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM B a n k 0 , 1 , 2 , 3 , 4 B a n k 0 , 2 , 3 , 4 B a n k 1 0 0 H I A R 0...
Page 38: Special Function Register Description
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are...
Page 39: Bank Pointer - Bp
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Indirect Addressing Program Example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block...
Page 40 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM BP Register • HT66F20/HT66F40 Name — — — — — — — DMBP0 — — — — — — — — — — — — — — Bit 7~1 Unimplemented, read as "0" Bit 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 •...
Page 41 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading...
Page 42 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if...
Page 43 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM STATUS Register Name — — — — — — “x”: �nknown Bit 7, 6 Unimplemented, read as “0” Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. PDF: Power down flag Bit 4 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry...
Page 44: Eeprom Data Memory
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM EEPROM Data Memory The device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product...
Page 45 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM EEPROM Register List • HT66F20 Name — — — D� D� D� — — — — WREN RDEN • HT66F30 Name — — D� D� D� — — — — WREN RDEN • HT66F40 Name —...
Page 46 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F30 Name — — D� — — — — × × × × × × "x" �nknown Bit 7~6 Unimplemented, read as "0" Bit 5~0 Data EEPROM address Data EEPROM address bit 5~bit 0 • HT66F40 Name — D� — — × × ×...
Page 47 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM EEC Register Name — — — — WREN RDEN — — — — — — — — Bit 7~4 Unimplemented, read as "0" Bit 3 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data...
Page 48: Reading Data From The Eeprom
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is...
Page 49: Programming Considerations
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples Reading Data from the EEPROM – Polling Mothod MOV A, EEPROM_ADRES ; user defined address...
Page 50: Oscillators
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for theWatchdog Timer and Time Base Interrupts. External oscillators requiring some external...
Page 51 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM H i g h S p e e d O s c i l l a t o r H X T E R C 6 - s t a g e P r e s c a l e r...
Page 52: External Crystal/Ceramic Oscillator - Hxt
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturers specification. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the MCU as possible. I n t e r n a l O S C 1 O s c i l l a t o r...
Page 53: External Rc Oscillator - Erc
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM External RC Oscillator – ERC Using the ERC oscillator only requires that a resistor, with a value between 56kΩ and 2.4MΩ is connected between OSC1 and VDD, and a capacitor is connected between OSC1 and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a...
Page 54: External 32.�68Khz Crystal Oscillator - Lxt
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM External 32.768kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is required.
Page 55: Internal Low Speed Oscillator - Lirc
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the TBC register. LXTLP Bit LXT Mode Q�ick Start � Low-power After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Low-power mode. Internal Low Speed Oscillator – LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of...
Page 56: Operating Modes And System Clocks
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clock The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, f , or low frequency, f , source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT, ERC or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from internal clock f...
Page 57 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM H i g h S p e e d O s c i l l a t o r H X T E R C 6 - s t a g e P r e s c a l e r...
Page 58: System Operation Modes
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,...
Page 59: Control Register
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs and SIM. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, f , will either be on or off depending upon the f clock source. If the source is f /4 then the f clock will be off, and if the source comes from f then f will be on. • IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, f , will be on. If the source is f /4 then the f clock will be on, and if the source comes from f then f will be on. Control Register A single register, SMOD, is used for overall control of the internal clocks within the device.
Page 60 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 3 LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 2 HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator is used. IDLEN: IDLE Mode control bit 1 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed.
Page 61: Fast Wake-�P
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows f , namely either the LXT or LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is f , the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the FastWake-up function has no effect because the f clock is stopped. The FastWake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two t clock cycles of the LIRC or LXT oscillator for the system to wake-up. The system will then initially run under the f clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the ERC or HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the ERC or HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System FSTEN Wake-up Time Wake-up Time Wake-up Time...
Page 62: Operating Mode Switching
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, f , to the clock source, f /2~f /64 or f . If the clock is from the f , the high speed clock source will stop running to conserve power. When this happens it must be noted that the...
Page 63 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. N O R M A L M o d e C K S 2 ~ C K S 0 = 0 0 x B &...
Page 64 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110", or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. S L O W M o d e C K S 2 ~ C K S 0 ¹ 0 0 0 B , 0 0 1 B a s H L C L K = 0...
Page 65 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock, WDT clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped no matter if the WDT clock source originates from the f clock or from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at...
Page 66: Standby C�Rrent Considerations
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in WDTC register equal to “1”. When this instruction is executed under the with conditions described above, the following will occur: • The system clock and Time Base clock and f clock will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock source which originates from the f clock or from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.
Page 67: Programming Considerations
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Page 68: Watchdog Timer
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, f , which is in turn supplied by one of two sources selected by configuration option: f or f /4. The f clock can be sourced from either the LXT or LIRC oscillators, again chosen via a configuration option. The Watchdog Timer source clock is then subdivided by a ratio of 2 to 2 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with V , temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The other Watchdog Timer clock source option is the f /4 clock. The Watchdog Timer clock source can originate from its own internal LIRC oscillator, the LXT oscillator or f /4. It is divided by a value of 2 to 2 , using the WS2~WS0 bits in the WDTC register to obtain the required Watchdog Timer time-out period. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register together with several configuration options control the overall operation of...
Page 69: Watchdog Timer Operation
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Some of the Watchdog Timer options, such as enable/disable, clock source selection and clear instruction type are selected using configuration options. In addition to a configuration option to enable/disable the Watchdog Timer, there are also four bits, WDTEN3~WDTEN0, in the WDTC register to offer an additional enable/disable control of the Watchdog Timer. To disable the Watchdog Timer, as well as the configuration option being set to disable, the WDTEN3~WDTEN0 bits must also be set to a specific value of "1010". Any other values for these bits will keep the Watchdog Timer enabled, irrespective of the configuration enable/disable setting. After power on these bits will have the value of 1010. If theWatchdog Timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. Note that if the Watchdog Timer has been disabled, then any instruction relating to its operation will result in no operation. WDT Configuration Option WDTEN3~WDTEN0 Bits WDT Enable ×××× Enable WDT Disable Except �0�0 Enable WDT Disable �0�0...
Page 70: Reset And Initialisation
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM C L R W D T 1 F l a g C l e a r W D T T y p e C o n f i g u r a t i o n O p t i o n...
Page 71 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • RES Pin As the reset pin is shared with PB.0, the reset function must be selected using a configuration option. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time t is invoked to provide an extra delay time after RSTD which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
Page 72 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM When the reset pin is driven low by external hardware, most of the microcontroller pins will be forced into a high impedance condition. However special attention must be made to the PA5/ C1X/SDO/AN5 pin will be forced into a logical output low condition and PB2/OSC2 pin will be inverted by PB1/OSC1 pin when the reset pin is held low. For this reason it is recommended that these two pins are not connected to low impedance sources in the application circuit to eliminate the possibility of two low impedance sources being connected together. This situation only occurs when the reset pin is pulled low by external hardware and not during a power on or other reset type. Pin Name Pin Status PA5/C�X/SDO/AN5 O�tp�t Low PB2/OSC2 Inverted by PB�/OSC� Other pins High Impedance • Low Voltage Reset – LVR...
Page 73: Reset Initial Conditions
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: RESET Conditions Power-on reset � � RES or LVR reset d�ring NORMAL or SLOW Mode operation �...
Page 74 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Reset WDT Time-out WDT Time-out Register RES or LVR Reset (Power-on) (Normal Operation) (IDLE) MFI� - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - �...
Page 75 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM HT66F30 WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (IDLE) � x x x x x x x � x x x x x x x � x x x x x x x �...
Page 76 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (IDLE) TM0DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ��...
Page 77 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM HT66F40 WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (IDLE) x x x x x x x x x x x x x x x x x x x x x x x x �...
Page 78 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (IDLE) CP0C � 0 0 0 0 - - � � 0 0 0 0 - - � � 0 0 0 0 - - �...
Page 79 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM HT66F50 WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation (IDLE) x x x x x x x x x x x x x x x x x x x x x x x x �...
Page 80 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation (IDLE) ACERL � � � � � � � � � � � � � � � � � � � � � � � �...
Page 81 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM HT66F60 WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (IDLE) x x x x x x x x x x x x x x x x x x x x x x x x �...
Page 82 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (IDLE) ADCR0 0 �� 0 0 0 0 0 0 �� 0 0 0 0 0 0 �� 0 0 0 0 0 �...
Page 83: Input/Output Ports
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PG. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A,[m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Port Register List • HT66F20 Register Name PAWU D� D� PAPU D� D� D� D� D� D� PBPU — —...
Page 84 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F40/HT66F50 Register Name PAWU D� D� PAPU D� D� D� D� D� D� PBPU D� D� D� D� D� D� PCPU D� D� D� D� D� D� PDPU D� D� D� D�...
Page 85 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F60 Register Name PAWU D� D� PAPU D� D� D� D� D� D� PBPU D� D� D� D� D� D� PCPU D� D� D� D� D� D� PDPU D� D� D� D�...
Page 86: P�Ll-High Resistors
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PGPU, and are implemented using weak PMOS transistors. PAPU Register Name D� D� PBPU Register • HT66F40/HT66F50/HT66F60 Name D� D� PCPU Register • HT66F30/HT66F40/HT66F50/HT66F60 Name D�...
Page 87 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PFPU Register • HT66F60 Name D� D� Bit 7~0 I/O Port bit 7~bit 0 Pull-High Control 0: Disable 1: Enable PBPU Register • HT66F20/HT66F30 Name — — D� — — — — Bit 7~6 Unimplemented, read as “0” Bit 5~0 PBPU: Port B bit 5~bit 0 Pull-High Control 0: Disable 1: Enable PCPU Register • HT66F20 Name —...
Page 88: Port A Wake-�P
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PGPU Register • HT66F60 Name — — — — — — D� — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 PGPU: Port G bit 1~bit 0 Pull-High Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods...
Page 89 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PBC Register • HT66F40/HT66F50/HT66F60 Name D� D� � � � � � � � � PCC Register • HT66F30/HT66F40/HT66F50/HT66F60 Name D� D� � � � � � � � � PDC Register • HT66F40/HT66F50/HT66F60 Name D�...
Page 90 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PBC Register • HT66F20/HT66F30 Name — — D� — — � � � � � � — — Bit 7~6 Unimplemented, read as “0” Bit 5~0 PBC: Port B bit 5~bit 0 Input/Output Control 0: Output 1: Input PCC Register • HT66F20 Name — — — —...
Page 91: Pin-Remapping F�Nctions
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Pin-remapping Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Additionally there are a series of PRM0, PRM1 and PRM2 registers to establish certain pin functions. Pin-remapping Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. Some devices include PRM0, PRM1 or PRM2 registers which can select the functions of certain pins. Pin-remapping Register List • HT66F30 Register Name PRM0 — — — — — PCPRM SIMPS0 PCKPS • HT66F40...
Page 92 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PRM0 Register • HT66F30 Name — — — — — PCPRM SIMPS0 PCKPS — — — — — — — — — — Bit 7~3 Unimplemented, read as “0” Bit 2 PCPRM: PC1~PC0 pin-shared function Pin Remapping Control 0: No change 1: TP1B_0 on PC0 change to PA6, TP1B_1 on PC1 change to PA7 if SIMPS0=1 Bit 1 SIMPS0: SIM Pin Remapping Control 0: SDO on PA5; SDI/SDA on PA6; SCK/SCL on PA7; SCS on PB5 1: SDO on PC1; SDI/SDA on PC0; SCK/SCL on PC7; SCS on PC6...
Page 93 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PRM0 Register • HT66F60 Name C�XPS� C�XPS0 C0XPS� C0XPS0 PDPRM SIMPS� SIMPS0 PCKPS Bit 7~6 C1XPS1, C1XPS0: C1X Pin Remapping Control 00: C1X on PA5 01: C1X on PF1 10: C1X on PG1 11: Undefined Bit 5~4 C0XPS1, C0XPS0: C0X Pin Remapping Control 00: C0X on PA0 01: C0X on PF0 10: C0X on PG0 11: Undefined Bit 3 PDPRM: PD3~PD0 pin-shared function Pin Remapping Control 0: No change 1: TCK2 on PD0 change to PB6, TP2_0 on PD1 change to PB7, TCK0 on PD2 change to PD6, TCK1 on PD3 change to PD7 if SIMPS1, SIMPS0=01 or 11 Bit 2~1 SIMPS1, SIMPS0: SIM Pin Remapping Control 00: SDO on PA5; SDI/SDA on PA6; SCK/SCL on PA7; SCS on PB5...
Page 94 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PRM1 Register • HT66F40/HT66F50 Name TCK2PS TCK�PS TCK0PS — INT�PS� INT�PS0 INT0PS� INT0PS0 — — Bit 7 TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PD0 Bit 6 TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PD3 TCK0PS: TCK0 Pin Remapping Control Bit 5 0: TCK0 on PA2 1: TCK0 on PD2 Bit 4 Unimplemented, read as “0” Bit 3~2 INT1PS1, INT1PS0: INT1 Pin Remapping Control 00: INT1 on PA4...
Page 95 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PRM1 Register • HT66F60 Name TCK2PS TCK�PS TCK0PS INT2PS INT�PS� INT�PS0 INT0PS� INT0PS0 Bit 7 TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PD0 TCK1PS: TCK1 Pin Remapping Control Bit 6 0: TCK1 on PA4 1: TCK1 on PD3 TCK0PS: TCK0 Pin Remapping Control Bit 5 0: TCK0 on PA2 1: TCK0 on PD2 Bit 4 INT2PS: INT2 Pin Remapping Control 0: INT2 on PC4 1: INT2 on PE2 Bit 3~2 INT1PS1, INT1PS0: INT1 Pin Remapping Control 00: INT1 on PA4...
Page 96 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PRM2 Register • HT66F40 Name — — TP2�PS TP20PS TP�B2PS TP�APS TP0�PS TP00PS — — — — Bit 7~6 Unimplemented, read as “0” Bit 5 TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD4 Bit 4 TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD1 Bit 3 TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PE4 Bit 2 TP1APS: TP1A Pin Remapping Control...
Page 97 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PRM2 Register • HT66F50/HT66F60 Name TP3�PS TP30PS TP2�PS TP20PS TP�B2PS TP�APS TP0�PS TP00PS Bit 7 TP31PS: TP3_1 Pin Remapping Control 0: TP3_1 on PD0 1: TP3_1 on PE3 TP30PS: TP3_0 Pin Remapping Control Bit 6 0: TP3_0 on PD3 1: TP3_0 on PE5 TP21PS: TP2_1 Pin Remapping Control Bit 5 0: TP2_1 on PC4 1: TP2_1 on PD4 Bit 4 TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD1 Bit 3 TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PE4...
Page 98 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. P u l l - H i g h R e g i s t e r C o n t r o l B i t...
Page 99: Timer Modules - Tm
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PGC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PG, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port Ahas the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules,...
Page 100: Tm Operation
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM units which are shown in the table together with their individual reference name, TM0~TM3. Device HT66F20 �0-bit CTM �0-bit STM — — HT66F30 �0-bit CTM �0-bit ETM — — HT66F40 �0-bit CTM �0-bit ETM �6-bit STM — HT66F50 �0-bit CTM �0-bit ETM �6-bit STM �0-bit CTM...
Page 101: Tm External Pins
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or more output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. Asingle bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table. All TM output pin names have an "_n" suffix. Pin names that include a "_1" or "_2" suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits.
Page 102 T 1 C P 1 ( S T M ) T 1 C P 0 T C K I n p u t P A 4 / T C K 1 HT66F20 TM Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 2.50 �02...
Page 103 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P A 0 O u t p u t F u n c t i o n P A 0 / T P 0 _ 0 T 0 C P 0 P A 0...
Page 104 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P A 0 O u t p u t F u n c t i o n P A 0 / T P 0 _ 0 T 0 C P 0 P A 0...
Page 105 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P A 1 O u t p u t F u n c t i o n P A 1 / T P 1 A C C R A O u t p u t...
Page 106 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P A 0 O u t p u t F u n c t i o n P A 0 / T P 0 _ 0 T 0 C P 0 P A 0...
Page 107 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P A 1 O u t p u t F u n c t i o n P A 1 / T P 1 A C C R A O u t p u t...
Page 108 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TMPC0 Register • HT66F20 Name — — T�CP� T�CP0 — — — T0CP0 — — — — — � — — — � — — Bit 7~6 Unimplemented, read as “0” Bit 5 T1CP1: TP1_1 pin Control 0: Disable 1: Enable Bit 4 T1CP0: TP1_0 pin Control...
Page 109 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F40/HT66F50/HT66F60 Name T�ACP0 T�BCP2 T�BCP� T�BCP0 — — T0CP� T0CP0 — — � � — — � Bit 7 T1ACP0: TP1A pin Control 0: Disable 1: Enable T1BCP2: TP1B_2 pin Control Bit 6 0: Disable 1: Enable Bit 5 T1BCP1: TP1B_1 pin Control 0: Disable 1: Enable Bit 4 T1BCP0: TP1B_0 pin Control 0: Disable...
Page 110 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TMPC1 Register • HT66F40 Name — — — — — — T2CP� T2CP0 — — — — — — � — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1 T2CP1: TP2_1 pin Control 0: Disable 1: Enable Bit 0...
Page 111: Programming Considerations
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Programming Considerations The TM Counter Registers and the Capture/Compare CCRAand CCRB registers, being either 10- bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. TM Counter Register (Read only) TMxDL TMxDH 8-bit Buffer TMxAL TMxAH TM CCRA Register (Read/Write) TMxBL TMxBH TM CCRB Register (Read/Write) Data As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRB low byte registers, named TMxAL and TMxBL, using the following access procedures. Accessing the CCRA or CCRB low byte registers...
Page 112: Compact Type Tm - Ctm
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins. These two external output pins can be the same signal or the inverse signal. Name TM No. TM Input Pin TM Output Pin HT66F20 �0-bit CTM...
Page 113: Compact Type Tm Register Description
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Register Name TMnC0 TnPAU TnCK2 TnCK� TnCK0 TnON TnRP2 TnRP� TnRP0 TMnC� TnM� TnM0 TnIO�...
Page 114 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TMnC0 Register Name TnPAU TnCK2 TnCK� TnCK0 TnON TnRP2 TnRP� TnRP0 Bit 7 TnPAU: TMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 TnCK2~TnCK0: Select TMn Counter clock 000: f 001: f 010: f 011: f 100: f 101: Undefined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source f...
Page 115 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TMnC1 Register Name TnM� TnM0 TnIO� TnIO0 TnOC TnPOL TnDPX TnCCLR Bit 7~6 TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/counter Mode...
Page 116 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 3 TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active...
Page 117: Compact Type Tm Operating Modes
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to "00" respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the...
Page 118 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter overflow Co�nter Val�e TnCCLR = 0; TnM [�:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0x3FF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCRA Time TnON...
Page 119 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = �; TnM [�:0] = 00 CCRA = 0 CCRA > 0 Co�nter cleared by CCRA val�e Co�nter overflow 0x3FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRP Time TnON...
Page 120 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
Page 121 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 0; TnM [�:0] = �0 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns high CCRP Co�nter Stop if Pa�se Res�me TnON bit low CCRA Time TnON TnPAU TnPOL CCRA Int.
Page 122 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = �; TnM [�:0] = �0 Co�nter cleared by CCRA Co�nter Reset when TnON ret�rns high CCRA Co�nter Stop if Pa�se Res�me TnON bit low CCRP Time TnON TnPAU TnPOL CCRP Int.
Page 123: Standard Type Tm - Stm
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive two external output pins. Name TM No. TM Input Pin TM Output Pin HT66F20 �0-bit STM � TCK� TP�_0� TP�_� HT66F30 — — — — HT66F40 �6-bit STM TCK2 TP2_0�...
Page 124: Standard Type Tm Register Description
TM�DH — — — — — — TM�AL D� D� TM�AH — — — — — — 10-bit Standard TM Register List (for HT66F20) Register Name T2CK� T2CK0 T2ON — — — TM2C0 T2PAU T2CK2 TM2C� T2M� T2M0 T2IO� T2IO0...
Page 125 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 10-bit Standard TM Register List – HT66F20 • TM1C0 Register – 10-bit STM Name T�PAU T�CK2 T�CK� T�CK0 T�ON T�RP2 T�RP� T�RP0 Bit 7 T1PAU: TM1 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T1CK2~T1CK0: Select TM1 Counter clock Bit 6~4...
Page 126 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • TM1C1 Register – 10-bit STM Name T�M� T�M0 T�IO� T�IO0 T�OC T�POL T�DPX T�CCLR Bit 7~6 T1M1~T1M0: Select TM1 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T1IO1~T1IO0: Select TP1_0, TP1_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state...
Page 127 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 3 T1OC: TP1_0, TP1_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1POL: TP1_0, TP1_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1_0 or TP1_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode.
Page 128 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • TM1DL Register – 10-bit STM Name D� D� Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 • TM1DH Register – 10-bit STM Name — — — — — — — — — — — — — —...
Page 129 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 16-bit Standard TM Register List - HT66F40/HT66F50/HT66F60 • TM2C0 Register – 16-bit STM Name T2PAU T2CK2 T2CK� T2CK0 T2ON — — — — — — — — — Bit 7 T2PAU: TM2 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up...
Page 130 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • TM2C1 Register – 16-bit STM Name T2M� T2M0 T2IO� T2IO0 T2OC T2POL T2DPX T2CCLR Bit 7~6 T2M1~T2M0: Select TM2 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T2M1 and T2M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T2IO1~T2IO0: Select TP2_0, TP2_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state...
Page 131 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 3 T2OC: TP2_0, TP2_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T2POL: TP2_0, TP2_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP2_0 or TP2_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode.
Page 132 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • TM2DL Register – 16-bit STM Name D� D� Bit 7~0 TM2DL: TM2 Counter Low Byte Register bit 7~bit 0 TM2 16-bit Counter bit 7~bit 0 • TM2DH Register – 16-bit STM Name D�5 D�4 D�3 D�2 D�� D�0 Bit 7~0 TM2DH: TM2 Counter High Byte Register bit 7~bit 0 TM2 16-bit Counter bit 15~bit 8 • TM2AL Register – 16-bit STM Name D�...
Page 133: Standard Type Tm Operating Modes
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0...
Page 134 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TnCCLR = 0; TnM[�:0] = 00 Co�nter Co�nter Val�e overflow CCRP = 0 CCRP > 0 Co�nter cleared by CCRP val�e 0x3FF/ CCRP > 0 0xFFFF CCRP Pa�se Res�me Co�nter Stop Reset CCRA...
Page 135 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TnCCLR = �; TnM[�:0] = 00 Co�nter Val�e CCRA = 0 CCRA > 0 Co�nter cleared by CCRA val�e Co�nter overflows 0x3FF/ 0xFFFF CCRA = 0 CCRA Pa�se Res�me Co�nter Stop Reset CCRP...
Page 136 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM...
Page 137 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • 10-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period CCRA D�ty �28 5�2 �68 �024 The PWM output period is determined by the CCRAregister value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. • 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0...
Page 138 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 0; TnM [�:0] = �0 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns high CCRP Co�nter Stop if Pa�se Res�me TnON bit low CCRA Time TnON TnPAU TnPOL CCRA Int.
Page 139 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = �; TnM [�:0] = �0 Co�nter cleared by CCRA Co�nter Reset when TnON ret�rns high CCRA Co�nter Stop if Pa�se Res�me TnON bit low CCRP Time TnON TnPAU TnPOL CCRP Int.
Page 140 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Single Pulse Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. L e a d i n g E d g e T r a i l i n g E d g e...
Page 141 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Counter Value TnM [1:0] = 10 ; TnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when TnON returns high CCRA Counter Stops Resume Pause by software CCRP Time TnON Auto. set by...
Page 142 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run. As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode. Rev. 2.50 �42 ��ne 22� 20��...
Page 143 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TnM [�:0] = 0� Co�nter Val�e Co�nter overflow CCRP Co�nter Stop Reset Pa�se Res�me Time TnON edge TnPAU Active Active Active edge edge TM Capt�re Pin TPn_x CCRA Int. Flag TnAF CCRP Int.
Page 144: Enhanced Type Tm - Etm
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Enhanced Type TM – ETM The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins. Name TM No. TM Input Pin TM Output Pin HT66F20 — — — — HT66F30 �0-bit ETM � TCK� TP�A; TP�B_0� TP�B_� HT66F40 �0-bit ETM �...
Page 145: Enhanced Tm Operation
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Enhanced TM Operation At its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. There are three internal comparators with the names, Comparator A, Comparator B and Comparator P. These comparators will compare the value in the counter with the CCRA, CCRB and CCRP registers. The CCRP comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while CCRA and CCRB are 10-bits wide and therefore compared with all counter bits.
Page 146 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 10-bit Enhanced TM Register List – HT66F30/HT66F40/HT66F50/HT66F60 • TM1C0 Register – 10-bit ETM Name T�PAU T�CK2 T�CK� T�CK0 T�ON T�RP2 T�RP� T�RP0 Bit 7 T1PAU: TM1 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T1CK2~T1CK0: Select TM1 Counter clock Bit 6~4...
Page 147 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • TM1C1 Register – 10-bit ETM Name T�AM� T�AM0 T�AIO� T�AIO0 T�AOC T�APOL T�CDN T�CCLR Bit 7~6 T1AM1~T1AM0: Select TM1 CCRA Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Page 148 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 3 T1AOC: TP1A Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1APOL: TP1A Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode.
Page 149 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • TM1C2 Register – 10-bit ETM Name T�BM� T�BM0 T�BIO� T�BIO0 T�BOC T�BPOL T�PWM� T�PWM0 Bit 7~6 T1BM1~T1BM0: Select TM1 CCRB Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Page 150 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 3 T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter...
Page 151 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • TM1DL Register – 10-bit ETM Name D� D� Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 • TM1DH Register – 10-bit ETM Name — — — — — — — — — — — — — —...
Page 152: Enhanced Type Tm Operating Modes
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • TM1BH Register – 10-bit ETM Name — — — — — — — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 TM1BH: TM1 CCRB High Byte Register bit 1~bit 0 TM1 10-bit CCRB bit 9~bit 8 Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The...
Page 153 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Compare Output Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator Aand Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator Aor Comparator B. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0, TPnB_1 or TPnB_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note that if the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place. Rev. 2.50 �53 ��ne 22� 20��...
Page 154 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter overflow Co�nter Val�e TnCCLR = 0; TnAM [�:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0x3FF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCRA Time TnON...
Page 155 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter overflow Co�nter Val�e TnCCLR = 0; TnBM [�:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0x3FF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCRB Time TnON...
Page 156 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = �; TnAM [�:0] = 00 CCRA = 0 CCRA > 0 Co�nter cleared by CCRA val�e Co�nter overflow 0x3FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRP Time TnON...
Page 157 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = �; TnBM [�:0] = 00 CCRA = 0 CCRA > 0 Co�nter cleared by CCRA val�e Co�nter overflow 0x3FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRB Time TnON...
Page 158 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 register should all be set high. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.
Page 159 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period �28 5�2 �68 �024 A D�ty CCRA B D�ty CCRB If f =16MHz, TM clock source select f /4, CCRP=100b, CCRA=128 and CCRB=256, The TP1A PWM output frequency=(f /4)/512=f /2048=7.8125kHz, duty=128/512=25%.
Page 160 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 0; Co�nter Cleared by CCRP TnAM [�:0] = �0� TnBM [�:0] = �0; TnPWM [�:0] = 00 CCRP CCRA Co�nter Res�me Stop Pa�se Restart CCRB Time TnON TnPAU TnAPOL CCRA Int.
Page 161 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = �; TnBM [�:0] = �0; Co�nter Cleared by CCRA TnPWM [�:0] = 00 CCRA Co�nter Res�me Stop Pa�se Restart CCRB Time TnON TnPAU TnBPOL CCRP Int. Flag TnPF CCRB Int.
Page 162 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 0; TnAM [�:0] = �0� TnBM [�:0] = �0; TnPWM [�:0] = �� CCRP Co�nter Stop Restart Res�me CCRA Pa�se CCRB Time TnON TnPAU TnAPOL CCRA Int. Flag TnAF CCRB Int.
Page 163 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = �; TnBM [�:0] = �0; TnPWM [�:0] = �� CCRA Co�nter Stop Restart Res�me Pa�se CCRB Time TnON TnPAU TnBPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int.
Page 164 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Single Pulse Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. The trigger for the pulse TPnB output leading edge is a compare match from Comparator B, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB. In this way the CCRA value can be used to control the pulse width of TPnA. The CCRA-CCRB value can be used to control the pulse width of TPnB. A compare match from Comparator A and Comparator B will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used. Counter Value CCRA...
Page 165 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnAM [�:0] = �0� TnBM [�:0] = �0; Co�nter stopped TnAIO [�:0] = �� TnBIO [�:0] = �� by CCRA Co�nter Reset CCRA when TnON ret�rns high Co�nter Stops Res�me Pa�se...
Page 166 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and TMnC2 registers. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated. Irrespective of what events occur on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits can select the active trigger edge on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins to be a rising edge, falling edge or both edge types. If the TnAIO1, TnAIO0 and TnBIO1, TnBIO0...
Page 167 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Co�nter Val�e TnAM [�:0] = 0� Co�nter cleared by CCRP Co�nter Co�nter Stop Reset CCRP Res�me Pa�se Time TnON TnPAU Active Active Active edge edge edge TM capt�re pin TPnA CCRA Int. Flag TnAF CCRP Int.
Page 168 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TnBM�� TnBM0 = 0� Co�nter Co�nter Val�e overflow CCRP Co�nter Stop Reset Pa�se Res�me Time TnON bit TnPAU bit Active Active Active edges edge edge TM Capt�re Pin CCRB Int. Flag TnBF CCRP Int.
Page 169: Aanlog To Digital Converter
D�� D�0 ADCR0 START EOCB ADOFF ADRFS — ACS2 ACS� ACS0 ADCR� ACS4 V�25EN — VREFS — ADCK2 ADCK� ADCK0 ACERL ACE� ACE6 ACE5 ACE4 ACE3 ACE2 ACE� ACE0 HT66F20/HT66F30/HT66F40/HT66F50 A/D Converter Register List Rev. 2.50 �69 ��ne 22� 20��...
Page 170 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Register Name ADRL(ADRFS=0) D� — — — — ADRL(ADRFS=�) D� D� ADRH(ADRFS=0) D�� D�0 D� ADRH(ADRFS=�) — — — — D�� D�0 ADCR0 START EOCB ADOFF ADRFS ACS3 ACS2 ACS� ACS0 ADCR� ACS4 V�25EN...
Page 171 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM ADCR0 Register • HT66F20/HT66F30/HT66F40/HT66F50 Name START EOCB ADOFF ADRFS — ACS2 ACS� ACS0 — � � — Bit 7 START: Start the A/D conversion 0→1→0: start 0→1: Reset the A/D converter and set EOCB to “1” This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running the bit will be high. ADOFF: ADC module power on/off control bit Bit 5 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared...
Page 172 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM ADCR0 Register • HT66F60 Name START EOCB ADOFF ADRFS ACS3 ACS2 ACS� ACS0 � � Bit 7 START: Start the A/D conversion 0→1→0: start 0→1: Reset the A/D converter and set EOCB to “1” This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running the bit will be high. ADOFF: ADC module power on/off control bit Bit 5 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will...
Page 173 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM ADCR1 Register Name ACS4 V�25EN — VREFS — ADCK2 ADCK� ADCK0 — — — — Bit 7 ACS4: Selecte Internal 1.25V as ADC input Control 0: Disable 1: Enable This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other A/D input channels disconnected. Bit 6 V125EN: Internal 1.25V Control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. When 1.25V is switched on for use by the A/D converter, a time t should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion.
Page 174 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM ACERL Register Name ACE� ACE6 ACE5 ACE4 ACE3 ACE2 ACE� ACE0 � � � � � � � � Bit 7 ACE7: Define PA7 is A/D input or not 0: Not A/D input 1: A/D input, AN7 ACE6: Define PA6 is A/D input or not Bit 6 0: Not A/D input 1: A/D input, AN6 Bit 5 ACE5: Define PA5 is A/D input or not 0: Not A/D input 1: A/D input, AN5 Bit 4 ACE4: Define PA4 is A/D input or not...
Page 175: A/D Operation
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock f , can be chosen to be either f or a subdivided version of f . The division ratio value is determined by the...
Page 176 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A, PE6, PF7, PF0 or PF1 as well as other functions. The ACE11~ACE0 bits in the ACERH and ACERL registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE11~ACE0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull- high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PAC, PEC or PFC port control register to enable the A/D input as when the ACE11~ACE0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of V P A 0 / A N 0 P F 1 / A N 1 1 1 .
Page 177 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16t where t is equal to the A/D clock period.
Page 178: Programming Considerations
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the V or V voltage, this gives a single bit analog input value of V or V divided by 4096. 1 LSB=(V or V )÷4096...
Page 179: A/D Programming Example
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select f /8 as A/D clock and switch off 1.25V clr ADOFF mov a,0Fh ; setup ACERL and ACERH to configure pins AN0~AN3...
Page 180 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select f 8 as A/D clock and switch off 1.25V SYS/ Clr ADOFF mov a,0Fh ; setup ACERL and ACERH to configure pins AN0~AN3 mov ACERL,a mov a,00h mov ACERH,00h ; ACERH is only for HT66F60 mov a,00h mov ADCR0,a ; enable and connect AN0 channel to A/D converter...
Page 181: Comparators
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Comparators Two independent analog comparators are contained within these devices. These functions offer flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused. C n P O L C n O U T C n + C n X C n - C n S E L Comparator Comparator Operation The device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. Full control over the two internal comparators...
Page 182: Comparator Registers
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Comparator Registers There are two registers for overall comparator operation, one for each comparator. As corresponding bits in the two registers have identical functions, they following register table applies to both registers. Register Name CP0C C0SEL C0EN C0POL C0OUT C0OS — — C0HYEN CP�C C�SEL C�EN C�POL...
Page 183 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 3 C0OS: Output path select 0: C0X pin 1: Internal use This is the comparator output path select control bit. If the bit is set to 0 and the C0SEL bit is 1 the comparator output is connected to an external C0X pin. If the bit is set to 1 or the C0SEL bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation.
Page 184: Comparator Interr
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 3 C1OS: Output path select 0: C1X pin 1: Internal use This is the comparator output path select control bit. If the bit is set to "0" and the C1SEL bit is "1" the comparator output is connected to an external C1X pin. If the bit is set to "1" or the C1SEL bit is "0" the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. Bit 2~1 Unimplemented, read as “0” Bit 0 C1HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
Page 185: Serial Interface Module - Sim
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four line SPI interface or the two line I C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected using a configuration option. As both interface types share the same pins and registers, the choice of whether the SPI or I C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O are selected using pull-high control registers, and also if the SIM function is enabled. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices.
Page 186 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. There are several configuration options associated with the SPI interface. One of these is to enable the SIM function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no effect. Another two SPI configuration options determine if the CSEN and WCOL bits are to be used. S P I M a s t e r S P I S l a v e...
Page 187 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I C interface. Register Name SIMC0 SIM2 SIM� SIM0 PCKEN PCKP� PCKP0 SIMEN — SIMD D� D� SIMC2 D� CKPOLB CKEG CSEN WCOL SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus...
Page 188 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • SIMC0 Register Name SIM2 SIM� SIM0 PCKEN PCKP� PCKP0 SIMEN — — � � � — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f 010: SPI master mode; SPI clock is f 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but...
Page 189 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • SIMC2 Register Name D� CKPOLB CKEG CSEN WCOL Bit 7~6 Undefined bit This bit can be read or written by user software program. CKPOLB: Determines the base condition of the clock line Bit 5 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit.
Page 190 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. S I M E N = 1 , C S E N = 0 ( E x t e r n a l P u l l - H i g h )
Page 191 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM S C S S C K ( C K P O L B = 1 ) S C K ( C K P O L B = 0 ) S D O D 7 / D 0...
Page 192: I 2 C Interface
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM C Interface The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. V D D S D A S C L D e v i c e...
Page 193 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM S T A R T s i g n a l f r o m M a s t e r S e n d s l a v e a d d r e s s...
Page 194 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • SIMC0 Register Name SIM2 SIM� SIM0 PCKEN PCKP� PCKP0 SIMEN — — � � � — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f 010: SPI master mode; SPI clock is f 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but...
Page 195 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • SIMC1 Register Name HAAS TXAK IAMWU RXAK � � Bit 7 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.
Page 196 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 0 RXAK: I C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is 0, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is 1. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I C Bus. The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I C functions. Before the device writes data to the I C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I C bus must be made via the SIMD register. • SIMD Register Name D� D� × × × × ×...
Page 197 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM D a t a B u s C D a t a R e g i s t e r S l a v e A d d r e s s R e g i s t e r...
Page 198 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM S t a r t S E T S I M [ 2 : 0 ] = 1 1 0 S E T S I M E N W r i t e S l a v e...
Page 199 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the C bus or write data to the I C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is 1 then this indicates that the master device wishes to read data from the I C bus, therefore the slave device must be setup to send data to the I C bus as a transmitter. If the SRW flag is 0 then this indicates that the master wishes to send data to the I C bus, therefore the slave device must be setup to read data from the I C bus as a receiver. C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The...
Page 200 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM S t a r t S l a v e A d d r e s s S R W A C K S C L S D A D a t a...
Page 201: Peripheral Clock Output
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal f clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to "1" enables the Peripheral Clock, setting PCKEN bit to "0" disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode this will disable the Peripheral Clock output. SIMC0 Register Name SIM2 SIM� SIM0 PCKEN PCKP� PCKP0 SIMEN — — � � � —...
Page 202: Interrupts
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0~INT3 and PINT pins, while the internal interrupts are generated by various internal functions such as the TMs, Comparators, Time Base, LVD, EEPROM, SIM and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain...
Page 203 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Interrupt Register Contents • HT66F20 Name INTEG — — — — INT�S� INT�S0 INT0S� INT0S0 INTC0 — CP0F INT�F INT0F CP0E INT�E INT0E INTC� MF�F MF0F CP�F MF�E MF0E CP�E INTC2 MF3F TB�F...
Page 204 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F50 Name INTEG — — — — INT�S� INT�S0 INT0S� INT0S0 INTC0 — CP0F INT�F INT0F CP0E INT�E INT0E INTC� MF�F MF0F CP�F MF�E MF0E CP�E INTC2 MF3F TB�F TB0F MF2F MF3E TB�E...
Page 205 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM INTEG Register • HT66F20/HT66F30/HT66F40/HT66F50 Name — — — — INT�S� INT�S0 INT0S� INT0S0 — — — — — — — — Bit 7~4 Unimplemented, read as “0” Bit 3~2 INT1S1, INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges INT0S1, INT0S0: Interrupt edge control for INT0 pin Bit 1~0...
Page 206 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM INTC0 Register • HT66F20/HT66F30/HT66F40/HT66F50 Name — CP0F INT�F INT0F CP0E INT�E INT0E — — Bit 7 Unimplemented, read as “0” Bit 6 CP0F: Comparator 0 interrupt request flag 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4 INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3 CP0E: Comparator 0 interrupt control 0: Disable 1: Enable INT1E: INT1 interrupt control...
Page 207 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F60 Name — INT2F INT�F INT0F INT2E INT�E INT0E — — Bit 7 Unimplemented, read as “0” Bit 6 INT2F: INT2 interrupt request flag 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4 INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3 INT2E: INT2 interrupt control 0: Disable 1: Enable INT1E: INT1 interrupt control Bit 2 0: Disable...
Page 208 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM INTC1 Register • HT66F20/HT66F30/HT66F40/HT66F50 Name MF�F MF0F CP�F MF�E MF0E CP�E Bit 7 ADF: A/D Converter Interrupt Request Flag 0: No request 1: Interrupt request MF1F: Multi-function Interrupt 1 Request Flag Bit 6 0: No request 1: Interrupt request MF0F: Multi-function Interrupt 0 Request Flag Bit 5 0: No request 1: Interrupt request Bit 4 CP1F: Comparator 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 ADE: A/D Converter Interrupt Control 0: Disable 1: Enable Bit 2 MF1E: Multi-function Interrupt 1 Control...
Page 209 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F60 Name MF0F CP�F CP0F INT3F MF0E CP�E CP0E INT3E Bit 7 MF0F: Multi-function Interrupt 0 Request Flag 0: No request 1: Interrupt request CP1F: Comparator 1 Interrupt Request Flag Bit 6 0: No request 1: Interrupt request Bit 5 CP0F: Comparator 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4 INT3F: INT3 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 MF0E: Multi-function Interrupt 0 Control 0: Disable 1: Enable Bit 2 CP1E: Comparator 1 Interrupt Control...
Page 210 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM INTC2 Register • HT66F20/HT66F30/HT66F40/HT66F50 Name MF3F TB�F TB0F MF2F MF3E TB�E TB0E MF2E Bit 7 MF3F: Multi-function Interrupt 3 Request Flag 0: No request 1: Interrupt request TB1F: Time Base 1 Interrupt Request Flag Bit 6 0: No request 1: Interrupt request TB0F: Time Base 0 Interrupt Request Flag Bit 5 0: No request 1: Interrupt request Bit 4 MF2F: Multi-function Interrupt 2 Request Flag 0: No request 1: Interrupt request Bit 3 MF3E: Multi-function Interrupt 3 Control 0: Disable 1: Enable...
Page 211 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F60 Name MF3F MF2F MF�F MF3E MF2E MF�E Bit 7 ADF: A/D Converter Interrupt Request Flag 0: No request 1: Interrupt request MF3F: Multi-function Interrupt 3 Request Flag Bit 6 0: No request 1: Interrupt request Bit 5 MF2F: Multi-function Interrupt 2 Request Flag 0: No request 1: Interrupt request Bit 4 MF1F: Multi-function Interrupt 1 Request Flag 0: No request 1: Interrupt request Bit 3 ADE: A/D Converter Interrupt Control 0: Disable 1: Enable Bit 2 MF3E: Multi-function Interrupt 3 Control 0: Disable 1: Enable...
Page 212 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM INTC3 Register • HT66F60 Name MF5F TB�F TB0F MF4F MF5E TB�E TB0E MF4E Bit 7 MF5F: Multi-function interrupt 5 request flag 0: No request 1: Interrupt request TB1F: Time Base 1 interrupt request flag Bit 6 0: No request 1: Interrupt request TB0F: Time Base 0 interrupt request flag Bit 5 0: No request 1: Interrupt request Bit 4 MF4F: Multi-function interrupt 4 request flag 0: No request 1: Interrupt request Bit 3 MF5E: Multi-function interrupt 5 control 0: Disable 1: Enable...
Page 213 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM MFI0 Register • HT66F20/HT66F30 Name — — T0AF T0PF — — T0AE T0PE — — — — — — — — Bit 7~6 Unimplemented, read as “0” Bit 5 T0AF: TM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 T0PF: TM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0”...
Page 214 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM MFI1 Register • HT66F20 Name — — T�AF T�PF — — T�AE T�PE — — — — — — — — Bit 7~6 Unimplemented, read as “0” Bit 5 T1AF: TM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 T1PF: TM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0”...
Page 215 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM MFI2 Register Name SIMF SIME Bit 7 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request LVF: LVD interrupt request flag Bit 6 0: No request 1: Interrupt request Bit 5 XPF: External peripheral interrupt request flag 0: No request 1: Interrupt request Bit 4 SIMF: SIM interrupt request flag 0: No request 1: Interrupt request Bit 3 DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable Bit 2 LVE: LVD Interrupt Control 0: Disable 1: Enable XPE: External Peripheral Interrupt Control Bit 1 0: Disable 1: Enable...
Page 216: Interr�Pt Operation
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A or Comparator B match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own...
Page 217: M�Lti-F�Nction Interr�Pt
M. F�nct. 2 MF2F MF2E PINT Pin Time Base 0 TB0F TB0E Time Base � TB�F TB�E EEPROM M. F�nct. 3 MF3F MF3E Interr�pts contained within M�lti-F�nction Interr�pts HT66F30 only Interrupt Structure – HT66F20/HT66F30 Rev. 2.50 2�� ne 22� 20��...
Page 218 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM EMI a�to disabled in ISR Legend Interr�pt Req�est Enable Master Vector Priority Req�est Flag – no a�to reset in ISR Name Flags Bits Enable High INT0 Pin INT0F INT0E Req�est Flag – a�to reset in ISR Enable Bit INT�...
Page 219 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM EMI auto disabled in ISR Interrupt Request Enable Master Vector Priority Name Flags Bits Enable High INT0 Pin INT0F INT0E Legend Request Flag – no auto reset in ISR INT1 Pin INT1F INT1E Request Flag –...
Page 220 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT3. An external interrupt request will take place when the external interrupt request flags, INT0F~INT3F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT3E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT3F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Comparator Interrupt The comparator interrupt is controlled by the two internal comparators. A comparator interrupt request will take place when the comparator interrupt request flags, CP0F or CP1F, are set, a situation that will occur when the comparator output bit changes state. To allow the program to...
Page 221 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupt The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source f . This f...
Page 222 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TBC Register Name TBON TBCK TB�� TB�0 LXTLP TB02 TB0� TB00 � � � � � Bit 7 TBON: TB0 and TB1 Control 0: Disable 1: Enable TBCK: Select f Bit 6 Clock 0: f 1: f Bit 5~4 TB11~TB10: Select Time Base 1 Time-out Period 00: 4096/f 01: 8192/f 10: 16384/f 11: 32768/f Bit 3 LXTLP: LXT Low Power Control...
Page 223 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bits, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function Interrupt. A Peripheral Interrupt request will take place when the External Peripheral Interrupt request flag, XPF, is set, which occurs when a negative edge transition appears on the PINT pin. To allow the program to branch to its respective interrupt vector address, the...
Page 224 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupts The Compact and Standard Type TMs have two interrupts each, while the Enhanced Type TM has three interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. For the Enhanced Type TM there are three interrupt request flags TnPF, TnAF and TnBF and three enable bits TnPE, TnAE and TnBE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P, A or B match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match...
Page 225: Programming Considerations
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program.
Page 226: Low Voltage Detector - Lvd
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V , and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Name — — LVDO LVDEN — VLVD2 VLVD�...
Page 227: Lvd Operation
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.4V. When the power supply voltage, V , falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay t should be allowed for the circuitry to stabilise before reading the LVDS LVDO bit. Note also that as the V voltage may rise and fall rather slowly, at the voltage nears that of V , there may be multiple bit LVDO transitions. V D D L V D L V D E N L V D O L V D S...
Page 228: Scom Function For Lcd
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SCOM Function for LCD The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, are pin shared with certain pin on the PC0~PC3 or PC0~PC1, PC6~PC7 port. The LCD signals (COM and SEG) are generated using the application program. LCD Operation An external LCD panel can be driven using this device by configuring the PC0~PC3 or PC0~PC1, PC6~PC7 pins as common pins and using other output ports lines as segment pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary V /2 voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver, however this bit is used in conjunction with the COMnEN bits to select which Port C pins are used for LCD driving. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. S C O M o p e r a t i n g c u r r e n t...
Page 229: Lcd Bias Control
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM LCD Bias Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register. SCOMC Register • HT66F20 Name D� ISEL� ISEL0 SCOMEN COM3EN COM2EN COM�EN COM0EN Bit 7 Reserved Bit 0: Correct level - bit must be reset to zero for correct operation 1: Unpredictable operation - bit must not be set high ISEL1, ISEL0: Select SCOM typical bias current (V Bit 6~5 =5V) 00: 25μA 01: 50μA 10: 100μA 11: 200μA SCOMEN: SCOM module Control Bit 4...
Page 230 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • HT66F30/HT66F40/HT66F50/HT66F60 Name D� ISEL� ISEL0 SCOMEN COM3EN COM2EN COM�EN COM0EN Bit 7 Reserved Bit 0: Correct level - bit must be reset to zero for correct operation 1: Unpredictable operation - bit must not be set high ISEL1, ISEL0: Select SCOM typical bias current (V Bit 6~5 =5V) 00: 25μA 01: 50μA 10: 100μA 11: 200μA SCOMEN: SCOM module control Bit 4 0: Disable 1: Enable Bit 3 COM3EN: PC7 or SCOM3 selection 0: GPIO 1: SCOM3 Bit 2 COM2EN: PC6 or SCOM2 selection...
Page 231: Configuration Options
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. Options Oscillator Options High Speed System Oscillator Selection – f �. HXT � 2. ERC 3. HIRC Low Speed System Oscillator Selection – f �. LXT 2.
Page 232: Application Circuits
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Options C Debo�nce Time Selection: �. No debo�nce �3 2. � system clock debo�nce 3. 2 system clock debo�nce Application Circuits 0 . 0 1 m F * * V D D R e s e t...
Page 233: Uart Module Serial Interface
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM UART Module Serial Interface UART Module Features • Interconnected to Holtek MCU via SPI interface • Full-duplex, Universal Asynchronous Receiver and Transmitter (UART) communication 8 or 9 bit character length ♦ Even, odd or no parity options ♦ One or two stop bits ♦ Baud rate generator with 8-bit prescaler ♦ Parity, framing, noise and overrun error detection ♦ Support for interrupt on address detect ♦ Address Detect Interrupt - last character bit=1 ♦ Transmitter and receiver enabled independently ♦ 4-byte deep FIFO receiver data buffer ♦ Transmit and Receive Multiple Interrupt Generation Sources: ♦ – Transmitter Empty –...
Page 234: Pin Assignment
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Pin Assignment P A 1 / T P 1 A / A N 1 P A 0 / C 0 X / T P 0 _ 0 / A N 0 V S S & A V S S...
Page 235 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM P B 5 / S C S / V R E F P B 5 / S C S / V R E F P D 4 / [ T P 2 _ 1 ]...
Page 236 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM UART Module Pin Description Pin Name Description External UART RX serial data inp�t pin If UARTEN=� and RXEN=�� then RX is the UART serial data inp�t If UARTEN=0 or RXEN=0� then RX is high impedance External UART TX serial data o�tp�t pin...
Page 237 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM UART Module D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions =�2MHz� SCK=f /4� CLKI CLKI 3.0V — — �.0 O�tp�t no load Operating C�rrent * DD� (SPI Enabled� UART disabled) =�6MHz�...
Page 238 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM UART Module A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions 3.0V — 62.5 — — SCK Period (t 5.0V — 50.0 — — 3.0V — — — SCK High Time 5.0V...
Page 239 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM V D D V D D S C K S C K S D O S D I S D I S D O M C U U A R T M o d u l e...
Page 240: Uart Data Transfer Scheme
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM To initiate a data transaction, the MCU master SPI needs to pull SCS to a low level first and then also pull SCK low. The input data bit on SDI should be stable before the next SCK rising edge, as the device will latch the SDI status on the next SCK rising edge. Regarding the SDO line, the output data bit will be updated on the SCK falling edge. The master needs to obtain the line status before the next SCK falling edge. There are 16 bits of data transmitted and/or received by the SPI interface for each transaction. Each transaction consists of a command phase and a data phase. When SCS is high, the SPI interface is disabled and SDO will be set to a high impedance state. After a complete transaction has been implemented, which requires 16 SCK clock cycles, the master needs to set SCS to a high level in preparation for the next data transaction. For write operations, the device will begin to execute the command only after it receives a 16-bit serial data sequence and when the SCS has been set high again by the master. For read operations, the device will begin to execute the command only after it receives an 8-bit read command after which it will be ready to output data. If necessary, the master can de-assert the SCS pin to abort the transaction at any time which will cause any data transactions to be abandoned. UART Module External Pin Interfacing To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter serial data output pin if the corresponding control bits named UARTEN in UCR1 register and TXEN in UCR2 register are set to 1. If the control bit UARTEN or TXEN is equal to zero, the TX pin is in the state of high impedance. Similarly, the RX pin is the UART receiver serial data input pin if the corresponding control bits named UARTEN and RXEN in UCR1 and UCR2 registers are set to 1. If the control bit UARTEN or RXEN is equal to zero, the RX pin is in the state of high impedance. UART Data Transfer Scheme The following block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmitter Shift Register named TSR...
Page 241: Uart Commands
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Transmitter Shift Register (TSR) Receiver Shift Register (RSR) TX Pin RX Pin ………………………… ………………………… B�ffer 3 B�ffer 2 B�ffer � Ba�d Rate Generator TX Register (TXR) RX Register (RXR) Data to be transmitted...
Page 242 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM USR Register The USR register is the status register for the UART, which can be read by the application program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: Name PERR FERR OERR RIDLE RXIF TIDLE TXIF � � � PERR: Parity error flag Bit 7 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is 0, it indicates a parity error has not been detected. When the flag is 1, it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NR flag is the noise flag. When this read only flag is 0, it indicates no noise condition. When the flag is 1, it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence...
Page 243 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 2 RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is 0, it indicates that the RXR read data register is empty. When the flag is 1, it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1 TIDLE: Transmission idle 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is 0, it indicates that a transmission is in progress. This flag will be set to 1 when the TXIF flag is 1 and when there is no transmit data or break character being transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0 TXIF: Transmit TXR data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is 0, it indicates that the character is not transferred to the transmitter shift register. When the flag is 1, it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR)
Page 244 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function such as overall on/off control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below: Name UARTEN PREN STOPS TXBRK × “×” �nknown Bit 7 UARTEN: UART function enable control 0: Disable UART. TX and RX pins are in the state of high impedance 1: Enable UART. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to 0, the UART will be disabled and the RX pin as well as the TX pin will be in the state of high impedance. When the bit is equal to 1, the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. BNO: Number of data transfer bits selection Bit 6 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to 1, a 9-bit data length format will be selected.
Page 245 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 2 TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is 0, there are no break characters and the TX pin operates normally. When the bit is 1, there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to 1, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. RX8: Receive data bit 8 for 9-bit data transfer format (read only) Bit 1 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0 TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. UCR2 register The UCR2 register is the second of the UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable.
Page 246 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Bit 5 BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART. If this bit is equal to 1, the high speed mode is selected. If the bit is equal to 0, the low speed mode is selected. ADDEN: Address detect function enable control Bit 4 0: Address detect function is disabled 1: Address detect function is enabled The bit named ADDEN is the address detect function enable control bit. When this bit is equal to 1, the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, has a value of 1, then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the received word is 0 with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. WAKE: RX pin falling edge wake-up function enable control Bit 3 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or disables the receiver wake-up function. If this bit is equal to 1 and the MCU is in IDLE or SLEEP mode, a falling edge on the RX input pin will wake-up the device. If this bit is equal to 0 and the MCU is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake-up the device. Bit 2 RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to 1 and when...
Page 247 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM UCR3 register The UCR3 register is the last of the UART control registers and controls the software reset operation of the UART module. The only one available bit named URST in the UART control register UCR3 is the UART software reset control bit. When this bit is equal to 0, the UART operates normally. If this bit is equal to 1, the whole UART module will be reset. When this situation occurs, the transmitter and receiver will be reset. The UART registers including the status register and control registers will keep the POR states shown in the above UART registers table after the reset condition occurs. Name URST — — — — — — — — — — — — — — — — — — — — — Bit 7...
Page 248 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • Calculating the baud rate and error values For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. CLKI From the above table the desired baud rate BR= [64 (N+1)] CLKI −1 Re-arranging this equation gives N= (BR×64) 4000000 −1 Giving a value for N= =12.0208 (4800×64) To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of 4000000 =4808 [64 (12+1)] 4808−4800 Therefore the error is equal to =0.16% 4800 The following tables show the actual values of baud rate and error values for the two value of BRGH. Baud Rates for BRGH=0...
Page 249 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM BRG Register Name BRG� BRG6 BRG5 BRG4 BRG3 BRG2 BRG� BRG0 × × × × × × × × “×” �nknown Bit 7~0 BRG7~BRG0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup.
Page 250 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • Data, parity and stop bit selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9. The PRT bit controls the choice if odd or even parity. The PREN bit controls the parity on/off function. The STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address detect mode control bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats � � � � � � � �...
Page 251 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit LSB first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required ♦ word length, parity type and number of stop bits. Setup the BRG register to select the desired baud rate. ♦ Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a ♦ UART transmitter pin. Access the USR register and write the data that is to be transmitted into the TXR register. Note ♦ that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access...
Page 252 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • UART receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. • Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin to the shift register, with the least significant bit LSB first. The RXR register is a four byte...
Page 253 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • Receiving break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: The framing error flag, FERR, will be set. ♦ The receive data register, RXR, will be cleared. ♦ The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. ♦ • Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. • Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1.
Page 254: Managing Receiver Errors
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. • Overrun Error – OERR flag The RXR register is composed of a four byte deep FIFO data buffer, where four bytes can be held in the FIFO register, while a 5th byte can continue to be received. Before the 5th byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: The OERR flag in the USR register will be set. ♦ The RXR contents will not be lost. ♦ The shift register will be overwritten. ♦ An interrupt will be generated if the RIE bit is set. ♦ The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. • Noise Error – NF flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame, the following will occur: The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. ♦ Data will be transferred from the shift register to the RXR register. ♦ No interrupt will be generated. However this bit rises at the same time as the RXIF bit which ♦ itself generates an interrupt.
Page 255 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM UART Module Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated on the INT line to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the UART module is woken up by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of...
Page 256 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Address detect mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this special function. If this bit is set to 1, then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is equal to 1, then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the 9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last but status. The address detect and parity functions are mutually exclusive functions. Therefore if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. Bit 9 (BNO=1) UART Interrupt ADDEN Bit 8 (BNO=0) Generated √ � √ × � � √...
Page 257 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Using the UART Function To use the UART function, several important steps must be implemented to ensure that the UART module operates normally: • The SPI pin-remapping function must be properly configured when the SPI functional pins of the microcontroller are used to control the UART module and for data transmission and data reception. To correctly connect the MCU Master SPI to the UART Module Slave SPI, the SIM pin-remapping settings for PCK and PINT in the MCU PRM0 register should be the same as the values listed in the following table. HT66FU30 ♦ – PRM0 Register – PCK and PINT pin-remap setup Name SIMPS0 PCKPS Setting val�e � � HT66FU40/HT66FU50 ♦ – PRM0 Register – PCK and PINT pin-remap setup Name SIMPS� SIMPS0 PCKPS Setting val�e �...
Page 258 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM • The PCK control bit is set to 1 to enable the PCK output as the clock source for the UART baud rate generator with various PCK output frequencies determined by the PCKP1 and PCKP0 bits in the SIMC0 Register. PCK output frequency selection bits PCKP1~PCKP0 in the SIMC0 Register ♦ Name PCKP� PCKP0 val�e ��0�0��00 00: PCK output frequency is f 01: PCK output frequency is f 10: PCK output frequency is f 11: PCK output frequency is TM0 CCRP match frequency/2 PCK output enable control bit PCKEN in the SIMC0 Register ♦ Name PCKEN val�e � 0: Disable PCK output 1: Enable PCK output After the above setup conditions have been implemented, the MCU can enable the SIM interface by setting the SIMEN bit high. The MCU can then begin communication with external UART connected devices using its SPI interface. The detailed MCU Master SPI functional description is provided within the Serial Interface Module section of the MCU datasheet. Application Circuit with UART Module 0 . 0 1 m F * *...
Page 259: Instruction Set
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to...
Page 260: Logical And Rotate Operation
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...
Page 261: Instruction Set Summary
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A�[m] Add Data Memory to ACC � Z� C� AC� OV Note ADDM A�[m] Add ACC to Data Memory �...
Page 262 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Data Move MOV A�[m] Move Data Memory to ACC � None MOV [m]�A Move ACC to Data Memory � Note None MOV A�x Move immediate data to ACC �...
Page 263: Instruction Definition
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x...
Page 264 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None Clear Watchdog Timer CLR WDT Description The TO, PDF flags and the WDT are all cleared.
Page 265 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H Affected flag(s) DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1.
Page 266 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ← addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None Move immediate data to ACC MOV A,x Description The immediate data specified is loaded into the Accumulator. Operation ACC ← x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory.
Page 267 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ← Stack ACC ← x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ← Stack EMI ← 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 Affected flag(s) None...
Page 268 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None RRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0...
Page 269 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None Skip if increment Data Memory is 0...
Page 270 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None Swap nibbles of Data Memory with result in ACC SWAPA [m] Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The...
Page 271 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None...
Page 272: Package Information
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 2.50 2�2 ��ne 22� 20��...
Page 273: 6-Pin Dip (300Mil) O�Tline Dimensions
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 16-pin DIP (300mil) Outline Dimensions & & Fig1. Full Lead Packages Fig2. 1/2 Lead Packages See Fig 1 Dimensions in inch Symbol Min. Nom. Max. 0.�80 0.�90 0.800 0.240 0.250 0.280 0.��5 0.�30 0.�95...
Page 274 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM See Fig 2 − Type 1 Dimensions in inch Symbol Min. Nom. Max. 0.�45 0.�65 0.�85 0.2�5 0.285 0.295 0.�20 0.�35 0.�50 0.��0 0.�30 0.�50 0.0�4 0.0�8 0.022 0.045 0.050 0.060 — 0.� BSC —...
Page 275: 6-Pin Nsop (�50Mil) O�Tline Dimensions
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 16-pin NSOP (150mil) Outline Dimensions & Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.�54 BSC — 0.0�2 — 0.020 — 0.390 BSC — — — 0.069 — 0.050 BSC —...
Page 276 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 16-pin SSOP (150mil) Outline Dimensions & Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.�54 BSC — 0.008 — 0.0�2 C’ — 0.�93 BSC — — — 0.069 —...
Page 277 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 20-pin DIP (300mil) Outline Dimensions Fig1. Full Lead Packages Fig2. 1/2 Lead Packages See Fig 1 Dimensions in inch Symbol Min. Nom. Max. 0.980 �.030 �.060 0.240 0.250 0.280 0.��5 0.�30 0.�95 0.��5 0.�30...
Page 278 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM See Fig 2 Dimensions in inch Symbol Min. Nom. Max. 0.945 0.965 0.985 0.2�5 0.285 0.295 0.�20 0.�35 0.�50 0.��0 0.�30 0.�50 0.0�4 0.0�8 0.022 0.045 0.050 0.060 — 0.� BSC — 0.300 0.3�0...
Page 279 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 20-pin SOP (300mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.406 BSC — — 0.295 BSC — 0.0�2 — 0.020 C’ — 0.504 BSC — — — 0.�04 — 0.050 BSC —...
Page 280 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 20-pin SSOP (150mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.�55 BSC — 0.008 — 0.0�2 C’ — 0.34� BSC — — — 0.069 — 0.025 BSC —...
Page 281 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 24-pin SKDIP (300mil) Outline Dimensions " " Fig1. Full Lead Packages Fig2. 1/2 Lead Packages See Fig1 Dimensions in inch Symbol Min. Nom. Max. �.230 �.250 �.280 0.240 0.250 0.280 0.��5 0.�30 0.�95 0.��5...
Page 282 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM See Fig2 Dimensions in inch Symbol Min. Nom. Max. �.�60 �.�85 �.�95 0.240 0.250 0.280 0.��5 0.�30 0.�95 0.��5 0.�30 0.�50 0.0�4 0.0�8 0.022 0.045 0.060 0.0�0 — 0.� BSC — 0.300 0.3�0 0.325...
Page 283 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 24-pin SOP (300mil) Outline Dimensions " Dimensions in inch Symbol Min. Nom. Max. — 0.406 BSC — — 0.295 BSC — 0.0�2 — 0.020 C’ — 0.606 BSC — — — 0.�04 —...
Page 284 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 24-pin SSOP (150mil) Outline Dimensions " Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.�54 BSC — 0.008 — 0.0�2 C’ — 0.34� BSC — — — 0.069 —...
Page 285 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 28-pin SKDIP (300mil) Outline Dimensions & " Dimensions in inch Symbol Min. Nom. Max. �.380 — �.420 0.280 — 0.3�0 0.060 — 0.�30 0.�25 — 0.200 0.0�5 — 0.022 0.045 — 0.065 —...
Page 286 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 28-pin SOP (300mil) Outline Dimensions & " Dimensions in inch Symbol Min. Nom. Max. — 0.406 BSC — — 0.295 BSC — 0.0�2 — 0.020 C’ — 0.�05 BSC — — —...
Page 287 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 28-pin SSOP (150mil) Outline Dimensions & " Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.�54 BSC — 0.008 — 0.0�2 C’ — 0.390 BSC — — —...
Page 288 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SAW Type 32-pin (5mm×5mm) QFN Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. 0.028 0.030 0.03� A� 0.000 0.00� 0.002 — 0.008 REF — 0.00� 0.0�0 0.0�2 0.�93 0.�9� 0.20� 0.�93 0.�9�...
Page 289 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SAW Type 40-pin (6mm×6mm for 0.75mm) QFN Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. 0.028 0.030 0.03� A� 0.000 0.00� 0.002 — 0.008 REF — 0.00� 0.0�0 0.0�2 0.232 0.236 0.240 0.232...
Page 290 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 44-pin LQFP (10mm×10mm) (FP 2.0mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.4�2 BSC — — 0.394 BSC — — 0.4�2 BSC — — 0.394 BSC — — 0.03�5 BSC —...
Page 291 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 48-pin SSOP (300mil) Outline Dimensions " & " Dimensions in inch Symbol Min. Nom. Max. 0.395 — 0.42 0.29� 0.295 0.299 0.008 — 0.0�4 C’ 0.620 0.625 0.630 0.095 0.�02 0.�� — 0.025 BSC —...
Page 292 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM SAW Type 48-pin (7mm×7mm) QFN Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. 0.03� 0.033 0.035 A� 0.000 0.00� 0.002 — 0.008 REF — 0.008 0.0�0 0.0�2 — 0.2�6 BSC — —...
Page 293 HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Flash MCU with EEPROM 48-pin LQFP (7mm×7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.354 BSC — — 0.2�6 BSC — — 0.354 BSC — — 0.2�6 BSC — — 0.020 BSC — 0.00�...
Page 294 However� Holtek ass�mes no responsibility arising from the �se of the specifications described. The applications mentioned herein are used solely for the p�rpose of ill�stration and Holtek makes no warranty or representation that s�ch applications will be s�itable witho�t f�rther modification� nor recommends the �se of its prod�cts for application that may present a risk to h�man life d�e to...

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